Farley J. Abad

Array ( [id] => 20732302 [patent_doc_number] => 12639562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Quantized neural network circuit [patent_app_type] => utility [patent_app_number] => 19/179588 [patent_app_country] => US [patent_app_date] => 2025-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 3814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19179588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20094950 [patent_doc_number] => 20250224886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => SYSTEM AND METHOD FOR MAINFRAME APPLICATION ACCESS TO DATA STORED IN A NON-MAINFRAME ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 19/088536 [patent_app_country] => US [patent_app_date] => 2025-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19088536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20051994 [patent_doc_number] => 20250190216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => SYSTEMS AND METHODS FOR DATA PLACEMENT FOR IN-MEMORY-COMPUTE [patent_app_type] => utility [patent_app_number] => 19/060087 [patent_app_country] => US [patent_app_date] => 2025-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19060087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20181265 [patent_doc_number] => 20250265223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => Solver Based Buffer Depth Balancing for Dataflow AI Accelerator Architecture [patent_app_type] => utility [patent_app_number] => 19/055167 [patent_app_country] => US [patent_app_date] => 2025-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19055167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20152237 [patent_doc_number] => 20250252075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => Network on Chip with Data Movement Processing Cores [patent_app_type] => utility [patent_app_number] => 19/043790 [patent_app_country] => US [patent_app_date] => 2025-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5398 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19043790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20446895 [patent_doc_number] => 20260003617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => SYSTEMS AND METHODS OF PROGRAMMING FOR IN-MEMORY PROCESSING [patent_app_type] => utility [patent_app_number] => 19/038676 [patent_app_country] => US [patent_app_date] => 2025-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19038676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20738339 [patent_doc_number] => 20260147641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-28 [patent_title] => REUSABLE BARRIER FOR SYNCHRONIZATION AMONG MULTIPLE PROCESSES [patent_app_type] => utility [patent_app_number] => 19/037523 [patent_app_country] => US [patent_app_date] => 2025-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19037523 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20027036 [patent_doc_number] => 20250165258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => INSTRUCTION EXECUTION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 19/029760 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19029760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20101829 [patent_doc_number] => 20250231765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => NEURAL NETWORK COMPUTE TILE [patent_app_type] => utility [patent_app_number] => 19/024955 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19024955 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20095148 [patent_doc_number] => 20250225084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => PEER-TO-PEER MEMORY ACCESS REQUEST FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 19/008491 [patent_app_country] => US [patent_app_date] => 2025-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19008491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20089925 [patent_doc_number] => 20250219861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => PAGE-BASED REMOTE MEMORY ACCESS USING SYSTEM MEMORY INTERFACE NETWORK DEVICE [patent_app_type] => utility [patent_app_number] => 18/999934 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18999934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20797424 [patent_doc_number] => 20260178327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-25 [patent_title] => TRANSPOSE INSTRUCTIONS FOR 6-BIT FLOATING-POINT OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/999156 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18999156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20181247 [patent_doc_number] => 20250265205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => LOGIC DIE AND SEMICONDUCTOR DEVICE INCLUDING LOGIC DIE [patent_app_type] => utility [patent_app_number] => 18/988879 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18988879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20061752 [patent_doc_number] => 20250199974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => DATA STORAGE SYSTEM AND DATA STORING METHOD [patent_app_type] => utility [patent_app_number] => 18/972290 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18972290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19848893 [patent_doc_number] => 20250094244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => AUTOMATIC GRAPHICS PROCESSING UNIT SELECTION BASED ON KNOWN CONFIGURATION STATES [patent_app_type] => utility [patent_app_number] => 18/969027 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18969027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19804988 [patent_doc_number] => 20250070913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => QUALITY OF SERVICE AND STREAMING ATTRIBUTES FOR A DATA STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/941243 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18941243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20009455 [patent_doc_number] => 20250147677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SMART CABLE FOR CONNECTING STORAGE DRIVES [patent_app_type] => utility [patent_app_number] => 18/933352 [patent_app_country] => US [patent_app_date] => 2024-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18933352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20323297 [patent_doc_number] => 20250335385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => NETWORK PIPELINE ABSTRACTION LAYER (NAPL) SPLIT INTERFACES [patent_app_type] => utility [patent_app_number] => 18/928778 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19891906 [patent_doc_number] => 20250117218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => INSTRUCTIONS TO CONVERT FROM FP16 TO BF8 [patent_app_type] => utility [patent_app_number] => 18/927097 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18927097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19985659 [patent_doc_number] => 20250123881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING [patent_app_type] => utility [patent_app_number] => 18/927065 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 89539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18927065 [rel_patent_id] =>[rel_patent_doc_number] =>)