Farley J. Abad

Array ( [id] => 15369205 [patent_doc_number] => 20200020367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => MULTIPLE CONCURRENT MODULATION SCHEMES IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/530525 [patent_app_country] => US [patent_app_date] => 2019-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16530525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15027493 [patent_doc_number] => 20190324751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => TECHNOLOGIES FOR ENSURING FUNCTIONAL SAFETY OF AN ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/458018 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17605868 [patent_doc_number] => 11334356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Apparatuses, methods, and systems for a user defined formatting instruction to configure multicast Benes network circuitry [patent_app_type] => utility [patent_app_number] => 16/457994 [patent_app_country] => US [patent_app_date] => 2019-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 52 [patent_no_of_words] => 30454 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16706230 [patent_doc_number] => 10956162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Operand-based reach explicit dataflow processors, and related methods and computer-readable media [patent_app_type] => utility [patent_app_number] => 16/456836 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 15230 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16486324 [patent_doc_number] => 20200379930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => SYSTEM AND METHOD FOR TRANSFORMING LEGACY SR-IOV DEVICES TO APPEAR AS SIOV QUEUE PAIRS USING A MANAGEMENT CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/425803 [patent_app_country] => US [patent_app_date] => 2019-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16425803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16486161 [patent_doc_number] => 20200379766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => PROGRAM INSTRUCTION SCHEDULING [patent_app_type] => utility [patent_app_number] => 16/423290 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15257695 [patent_doc_number] => 20190377581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => PROCESSING APPARATUS AND CONTROLLING METHOD FOR PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/423898 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16470251 [patent_doc_number] => 20200371788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => VECTOR MAXIMUM AND MINIMUM WITH INDEXING [patent_app_type] => utility [patent_app_number] => 16/422501 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16470259 [patent_doc_number] => 20200371796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => VECTOR REVERSE [patent_app_type] => utility [patent_app_number] => 16/422795 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17877333 [patent_doc_number] => 11449347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => Time-multiplexed implementation of hardware accelerated functions in a programmable integrated circuit [patent_app_type] => utility [patent_app_number] => 16/421367 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 15707 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16421367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16943002 [patent_doc_number] => 11055244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-06 [patent_title] => Apparatus and method for simultaneous bidirectional serial lanes over USB-C interface [patent_app_type] => utility [patent_app_number] => 16/419585 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3059 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16145853 [patent_doc_number] => 10705997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => MIXDTAPE--cassette tape replica record/playback device [patent_app_type] => utility [patent_app_number] => 16/414632 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9628 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15373571 [patent_doc_number] => 10528504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Connection device restriction system [patent_app_type] => utility [patent_app_number] => 16/412550 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5582 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15257937 [patent_doc_number] => 20190377702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => I3C SINGLE DATA RATE WRITE FLOW CONTROL [patent_app_type] => utility [patent_app_number] => 16/405637 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16709022 [patent_doc_number] => 10958977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Systems, methods, and media for managing an entertainment system [patent_app_type] => utility [patent_app_number] => 16/403929 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7541 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16403929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14750761 [patent_doc_number] => 20190258554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => MONITOR PERIPHERAL DEVICE BASED ON IMPORTED DATA [patent_app_type] => utility [patent_app_number] => 16/402569 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16186131 [patent_doc_number] => 10719464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-21 [patent_title] => Lock circuit for competing kernels in a hardware accelerator [patent_app_type] => utility [patent_app_number] => 16/401104 [patent_app_country] => US [patent_app_date] => 2019-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5131 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15919485 [patent_doc_number] => 10656982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Apparatus and method for communicating data in a multi-tenant computer system [patent_app_type] => utility [patent_app_number] => 16/399286 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4077 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16628305 [patent_doc_number] => 20210046958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => COMPUTER INTERLOCKING SYSTEM AND SWITCHING CONTROL METHOD FOR THE SAME, DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/050808 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17050808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16292237 [patent_doc_number] => 10769088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => High performance computing (HPC) node having a plurality of switch coupled processors [patent_app_type] => utility [patent_app_number] => 16/371506 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 9704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16371506 [rel_patent_id] =>[rel_patent_doc_number] =>)