Search

Farley J. Abad

Examiner (ID: 5485, Phone: (571)270-3425 , Office: P/2181 )

Most Active Art Unit
2181
Art Unit(s)
2181
Total Applications
1109
Issued Applications
894
Pending Applications
94
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14629187 [patent_doc_number] => 20190227961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => NON-VOLATILE MEMORY OUT-OF-BAND MANAGEMENT INTERFACE FOR ALL HOST PROCESSOR POWER STATES [patent_app_type] => utility [patent_app_number] => 16/370494 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370494 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370494
Non-volatile memory out-of-band management interface for all host processor power states Mar 28, 2019 Issued
Array ( [id] => 14629191 [patent_doc_number] => 20190227963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => NETWORK-ON-CHIP FOR INTER-DIE AND INTRA-DIE COMMUNICATION IN MODULARIZED INTEGRATED CIRCUIT DEVICES [patent_app_type] => utility [patent_app_number] => 16/368688 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368688 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368688
Network-on-chip for inter-die and intra-die communication in modularized integrated circuit devices Mar 27, 2019 Issued
Array ( [id] => 14935389 [patent_doc_number] => 20190303332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => CIRCUIT DEVICE, ELECTRONIC DEVICE, AND CABLE HARNESS [patent_app_type] => utility [patent_app_number] => 16/367858 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16367858 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/367858
Circuit device, electronic device, and cable harness Mar 27, 2019 Issued
Array ( [id] => 16346285 [patent_doc_number] => 20200310936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => RECONFIGURABLE STAND ALONE DISTRIBUTED SYSTEM MOTOR CONTROLLERS [patent_app_type] => utility [patent_app_number] => 16/365931 [patent_app_country] => US [patent_app_date] => 2019-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16365931 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/365931
Reconfigurable stand alone distributed system motor controllers Mar 26, 2019 Issued
Array ( [id] => 14940691 [patent_doc_number] => 20190305984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => NETWORK NODE, NETWORK COMMUNICATION SYSTEM, AND NETWORK COMMUNICATION METHOD [patent_app_type] => utility [patent_app_number] => 16/364817 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364817 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364817
Network node, network communication system, and network communication method Mar 25, 2019 Issued
Array ( [id] => 14576215 [patent_doc_number] => 20190215716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => DETERMINING WHETHER A FLOW IS TO BE ADDED TO A NETWORK [patent_app_type] => utility [patent_app_number] => 16/358639 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358639 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358639
Determining whether a flow is to be added to a network Mar 18, 2019 Issued
Array ( [id] => 19566915 [patent_doc_number] => 12141689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Data compression for a neural network [patent_app_type] => utility [patent_app_number] => 16/357146 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14009 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16357146 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/357146
Data compression for a neural network Mar 17, 2019 Issued
Array ( [id] => 14571143 [patent_doc_number] => 20190213178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => METHODS AND SYSTEMS FOR DETERMINING HARDWARE SIZING FOR STORAGE ARRAY SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/355131 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16355131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/355131
Methods and systems for determining hardware sizing for storage array systems Mar 14, 2019 Issued
Array ( [id] => 16431414 [patent_doc_number] => 10831496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Method to execute successive dependent instructions from an instruction stream in a processor [patent_app_type] => utility [patent_app_number] => 16/288644 [patent_app_country] => US [patent_app_date] => 2019-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16288644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/288644
Method to execute successive dependent instructions from an instruction stream in a processor Feb 27, 2019 Issued
Array ( [id] => 16494251 [patent_doc_number] => 10860293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Efficient matrix data format applicable for artificial neural network [patent_app_type] => utility [patent_app_number] => 16/287564 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287564 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287564
Efficient matrix data format applicable for artificial neural network Feb 26, 2019 Issued
Array ( [id] => 16758493 [patent_doc_number] => 10977041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Offset-based mechanism for storage in global completion tables [patent_app_type] => utility [patent_app_number] => 16/286754 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5952 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286754 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286754
Offset-based mechanism for storage in global completion tables Feb 26, 2019 Issued
Array ( [id] => 16462743 [patent_doc_number] => 10846091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Coprocessor with distributed register [patent_app_type] => utility [patent_app_number] => 16/286213 [patent_app_country] => US [patent_app_date] => 2019-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286213 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286213
Coprocessor with distributed register Feb 25, 2019 Issued
Array ( [id] => 16431398 [patent_doc_number] => 10831480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Move data and set storage key instruction [patent_app_type] => utility [patent_app_number] => 16/283966 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283966 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283966
Move data and set storage key instruction Feb 24, 2019 Issued
Array ( [id] => 14750625 [patent_doc_number] => 20190258486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => EVENT-BASED BRANCHING FOR SERIAL PROTOCOL PROCESSOR-BASED DEVICES [patent_app_type] => utility [patent_app_number] => 16/281290 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281290
EVENT-BASED BRANCHING FOR SERIAL PROTOCOL PROCESSOR-BASED DEVICES Feb 20, 2019 Abandoned
Array ( [id] => 16462749 [patent_doc_number] => 10846097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Mispredict recovery apparatus and method for branch and fetch pipelines [patent_app_type] => utility [patent_app_number] => 16/281084 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7148 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281084 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281084
Mispredict recovery apparatus and method for branch and fetch pipelines Feb 19, 2019 Issued
Array ( [id] => 17565114 [patent_doc_number] => 20220129263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => TENSOR DECOMPOSITION PROCESSING SYSTEM, METHOD AND PROGRAM [patent_app_type] => utility [patent_app_number] => 17/430858 [patent_app_country] => US [patent_app_date] => 2019-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17430858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/430858
Tensor decomposition processing system, method and program Feb 19, 2019 Issued
Array ( [id] => 14473043 [patent_doc_number] => 20190188166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => INPUT DEVICE WITH MULTI-HOST SWITCHING [patent_app_type] => utility [patent_app_number] => 16/259849 [patent_app_country] => US [patent_app_date] => 2019-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259849 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/259849
Input device with multi-host switching Jan 27, 2019 Issued
Array ( [id] => 16887464 [patent_doc_number] => 20210173661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => AN ATTESTATION PROTOCOL BETWEEN A HOST SYSTEM AND A DATA PROCESSING ACCELERATOR [patent_app_type] => utility [patent_app_number] => 16/315987 [patent_app_country] => US [patent_app_date] => 2019-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16315987 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/315987
Attestation protocol between a host system and a data processing accelerator Jan 3, 2019 Issued
Array ( [id] => 14571085 [patent_doc_number] => 20190213149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => MODULE BASED DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 16/236971 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236971
Module based data transfer Dec 30, 2018 Issued
Array ( [id] => 14282393 [patent_doc_number] => 20190138481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => TECHNOLOGIES FOR PROVIDING DYNAMIC COMMUNICATION PATH MODIFICATION FOR ACCELERATOR DEVICE KERNELS [patent_app_type] => utility [patent_app_number] => 16/235982 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16235982 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/235982
Technologies for providing dynamic communication path modification for accelerator device kernels Dec 27, 2018 Issued
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