Farun Lu

Array ( [id] => 11273719 [patent_doc_number] => 20160336266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'SELF ALIGNED CONTACT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/219413 [patent_app_country] => US [patent_app_date] => 2016-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5479 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13405561 [patent_doc_number] => 20180254323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => SILICON CARBIDE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/754661 [patent_app_country] => US [patent_app_date] => 2016-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4557 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15754661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12574053 [patent_doc_number] => 10020279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Semiconductor device including built-in crack-arresting film structure [patent_app_type] => utility [patent_app_number] => 15/209269 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3210 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12396516 [patent_doc_number] => 09966430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) [patent_app_type] => utility [patent_app_number] => 15/202983 [patent_app_country] => US [patent_app_date] => 2016-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11517682 [patent_doc_number] => 20170084756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'STACKED NANOWIRE DEVICE WIDTH ADJUSTMENT BY GAS CLUSTER ION BEAM (GCIB)' [patent_app_type] => utility [patent_app_number] => 15/202994 [patent_app_country] => US [patent_app_date] => 2016-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14525803 [patent_doc_number] => 10340172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Semiconductor wafer surface protection film and method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/741564 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 11709 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15741564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13293091 [patent_doc_number] => 10157745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => High aspect ratio gates [patent_app_type] => utility [patent_app_number] => 15/196299 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5256 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12122476 [patent_doc_number] => 20180006062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'FIN-TYPE FIELD-EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/196353 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196353 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11109238 [patent_doc_number] => 20160306207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/196819 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11242 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11932761 [patent_doc_number] => 09799765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-24 [patent_title] => 'Formation of a bottom source-drain for vertical field-effect transistors' [patent_app_type] => utility [patent_app_number] => 15/196375 [patent_app_country] => US [patent_app_date] => 2016-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 5605 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11096560 [patent_doc_number] => 20160293529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'MANUFACTURING METHOD OF CHIP PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/186558 [patent_app_country] => US [patent_app_date] => 2016-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5436 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15186558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12375804 [patent_doc_number] => 09960162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Hybrid high-k first and high-k last replacement gate process [patent_app_type] => utility [patent_app_number] => 15/184405 [patent_app_country] => US [patent_app_date] => 2016-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12089075 [patent_doc_number] => 09842810 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-12 [patent_title] => 'Tiled-stress-alleviating pad structure' [patent_app_type] => utility [patent_app_number] => 15/176595 [patent_app_country] => US [patent_app_date] => 2016-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 8396 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11353692 [patent_doc_number] => 20160372432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'PACKAGE STRUCTURE AND METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/176384 [patent_app_country] => US [patent_app_date] => 2016-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 5411 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13653547 [patent_doc_number] => 09853095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 15/176293 [patent_app_country] => US [patent_app_date] => 2016-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6010 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13030625 [patent_doc_number] => 10037936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Semiconductor package with coated bonding wires and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 15/176163 [patent_app_country] => US [patent_app_date] => 2016-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2342 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11544841 [patent_doc_number] => 20170098666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'THIN FILM TRANSISTOR SUBSTRATE, DISPLAY APPARATUS INCLUDING THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE, AND METHOD OF MANUFACTURING DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/176510 [patent_app_country] => US [patent_app_date] => 2016-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8612 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13697887 [patent_doc_number] => 20170359898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => POWER DECOUPLING ATTACHMENT [patent_app_type] => utility [patent_app_number] => 15/176548 [patent_app_country] => US [patent_app_date] => 2016-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13173887 [patent_doc_number] => 10103066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Method of utilizing trench silicide in a gate cross-couple construct [patent_app_type] => utility [patent_app_number] => 15/167347 [patent_app_country] => US [patent_app_date] => 2016-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2982 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15167347 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11353755 [patent_doc_number] => 20160372495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'Dual-Gate Array Substrate, Display Panel and Display Device' [patent_app_type] => utility [patent_app_number] => 15/162714 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15162714 [rel_patent_id] =>[rel_patent_doc_number] =>)