Farun Lu

Array ( [id] => 11539515 [patent_doc_number] => 09613931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Fan-out stacked system in package (SIP) having dummy dies and methods of making the same' [patent_app_type] => utility [patent_app_number] => 14/701255 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5490 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14701255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11367020 [patent_doc_number] => 20170005001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'SEMICONDUCTOR WAFER, SEMICONDUCTOR DEVICE DICED FROM SEMICONDUCTOR WAFER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/125764 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14758 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15125764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11125352 [patent_doc_number] => 20160322326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-03 [patent_title] => 'WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIBUTION LAYER' [patent_app_type] => utility [patent_app_number] => 14/701049 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14701049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10455637 [patent_doc_number] => 20150340653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'OLED DISPLAY PANEL' [patent_app_type] => utility [patent_app_number] => 14/695458 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3407 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14695458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11542130 [patent_doc_number] => 20170095955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-06 [patent_title] => 'METHOD OF PRODUCING A HOUSING FOR AN ELECTRONIC DEVICE AND AN ELECTRONIC DEVICE, HOUSING FOR AN ELECTRONIC DEVICE, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/126071 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8329 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15126071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12355302 [patent_doc_number] => 09953946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Die-bonding layer formation film, processed product having die-bonding layer formation film attached thereto, and semiconductor device [patent_app_type] => utility [patent_app_number] => 15/125705 [patent_app_country] => US [patent_app_date] => 2015-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 15693 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15125705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14429679 [patent_doc_number] => 10319653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Semiconductor apparatus, stacked semiconductor apparatus, encapsulated stacked-semiconductor apparatus, and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/126172 [patent_app_country] => US [patent_app_date] => 2015-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 11861 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 495 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15126172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10378028 [patent_doc_number] => 20150263035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/632050 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10281338 [patent_doc_number] => 20150166335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'MEMS Package And A Method For Manufacturing The Same' [patent_app_type] => utility [patent_app_number] => 14/632428 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11014387 [patent_doc_number] => 20160211340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'IMPLANTATION FORMED METAL-INSULATOR-SEMICONDUCTOR (MIS) CONTACTS' [patent_app_type] => utility [patent_app_number] => 14/600077 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14600077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10463767 [patent_doc_number] => 20150348782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'APPARATUS FOR AND METHOD OF CRYSTALLIZING ACTIVE LAYER OF THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 14/600113 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4178 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14600113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14827895 [patent_doc_number] => 10410962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Encapsulated conformal electronic systems and devices, and methods of making and using the same [patent_app_type] => utility [patent_app_number] => 15/108861 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 38 [patent_no_of_words] => 14062 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15108861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10418274 [patent_doc_number] => 20150303284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'PUNCH THROUGH STOPPER IN BULK FINFET DEVICE' [patent_app_type] => utility [patent_app_number] => 14/578842 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10302771 [patent_doc_number] => 20150187771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'HYBRID HIGH-K FIRST AND HIGH-K LAST REPLACEMENT GATE PROCESS' [patent_app_type] => utility [patent_app_number] => 14/578732 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2592 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10302903 [patent_doc_number] => 20150187903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'FRINGE CAPACITANCE REDUCTION FOR REPLACEMENT GATE CMOS' [patent_app_type] => utility [patent_app_number] => 14/578722 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1920 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11187571 [patent_doc_number] => 09418982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-16 [patent_title] => 'Multi-layered integrated circuit with selective temperature coefficient of resistance' [patent_app_type] => utility [patent_app_number] => 14/578678 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11286435 [patent_doc_number] => 09502293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Self-aligned via process flow' [patent_app_type] => utility [patent_app_number] => 14/543992 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 26 [patent_no_of_words] => 3548 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10797029 [patent_doc_number] => 20160143185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'LIQUID-COOLED HEAT SINK ASSEMBLIES' [patent_app_type] => utility [patent_app_number] => 14/546159 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11153 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10451115 [patent_doc_number] => 20150336129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'MASK' [patent_app_type] => utility [patent_app_number] => 14/546237 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4601 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11265879 [patent_doc_number] => 09490181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-08 [patent_title] => 'Misalignment/alignment compensation method, semiconductor lithography system, and method of semiconductor patterning' [patent_app_type] => utility [patent_app_number] => 14/546645 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5151 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546645 [rel_patent_id] =>[rel_patent_doc_number] =>)