Search

Farun Lu

Examiner (ID: 3632, Phone: (571)270-0164 , Office: P/2898 )

Most Active Art Unit
2898
Art Unit(s)
2898
Total Applications
618
Issued Applications
575
Pending Applications
0
Abandoned Applications
47

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17566825 [patent_doc_number] => 20220130974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => Contact and Method for Making the Same [patent_app_type] => utility [patent_app_number] => 17/165448 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165448
Contact and Method for Making the Same Feb 1, 2021 Abandoned
Array ( [id] => 17752712 [patent_doc_number] => 20220230917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SELF-ALIGNED LATERAL CONTACT ELEMENTS AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/153972 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17153972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/153972
Three-dimensional memory device containing self-aligned lateral contact elements and methods for forming the same Jan 20, 2021 Issued
Array ( [id] => 17752932 [patent_doc_number] => 20220231137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => METAL CAP FOR CONTACT RESISTANCE REDUCTION [patent_app_type] => utility [patent_app_number] => 17/152190 [patent_app_country] => US [patent_app_date] => 2021-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152190
METAL CAP FOR CONTACT RESISTANCE REDUCTION Jan 18, 2021 Abandoned
Array ( [id] => 17752709 [patent_doc_number] => 20220230914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 17/149997 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149997 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149997
Semiconductor arrangement and method of making Jan 14, 2021 Issued
Array ( [id] => 17738236 [patent_doc_number] => 20220223698 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => WRAPAROUND CONTACT TO A BURIED POWER RAIL [patent_app_type] => utility [patent_app_number] => 17/148911 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148911 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148911
Wraparound contact to a buried power rail Jan 13, 2021 Issued
Array ( [id] => 18520763 [patent_doc_number] => 11710657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Middle-of-line interconnect structure having air gap and method of fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/147177 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 16814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147177 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147177
Middle-of-line interconnect structure having air gap and method of fabrication thereof Jan 11, 2021 Issued
Array ( [id] => 16981467 [patent_doc_number] => 20210225704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/135758 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135758
Method for fabricating a semiconductor device Dec 27, 2020 Issued
Array ( [id] => 17189134 [patent_doc_number] => 20210336019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => DRAIN SIDE RECESS FOR BACK-SIDE POWER RAIL DEVICE [patent_app_type] => utility [patent_app_number] => 17/123873 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123873
Drain side recess for back-side power rail device Dec 15, 2020 Issued
Array ( [id] => 19063117 [patent_doc_number] => 11942367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 17/113836 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113836 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113836
Semiconductor device and method of manufacture Dec 6, 2020 Issued
Array ( [id] => 17417264 [patent_doc_number] => 20220052168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => COMMON RAIL CONTACT [patent_app_type] => utility [patent_app_number] => 17/112782 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17112782 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/112782
Common rail contact Dec 3, 2020 Issued
Array ( [id] => 16724087 [patent_doc_number] => 20210091234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => Transistors Comprising At Least One of GaP, GaN, and GaAs [patent_app_type] => utility [patent_app_number] => 17/111956 [patent_app_country] => US [patent_app_date] => 2020-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111956
Transistors comprising at least one of GaP, GaN, and GaAs Dec 3, 2020 Issued
Array ( [id] => 18416034 [patent_doc_number] => 11670581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Interconnect structure [patent_app_type] => utility [patent_app_number] => 17/104760 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104760
Interconnect structure Nov 24, 2020 Issued
Array ( [id] => 17373938 [patent_doc_number] => 20220028990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/104218 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104218
Semiconductor structure and method for forming the same Nov 24, 2020 Issued
Array ( [id] => 17956338 [patent_doc_number] => 11482451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Interconnect structures [patent_app_type] => utility [patent_app_number] => 16/949953 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949953 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949953
Interconnect structures Nov 19, 2020 Issued
Array ( [id] => 18016518 [patent_doc_number] => 11508826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Composite work function layer formation using same work function material [patent_app_type] => utility [patent_app_number] => 16/952503 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952503
Composite work function layer formation using same work function material Nov 18, 2020 Issued
Array ( [id] => 17615444 [patent_doc_number] => 20220157724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING OXIDATION-RESISTANT CONTACT STRUCTURES AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/952526 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952526
Three-dimensional memory device containing oxidation-resistant contact structures and methods of making the same Nov 18, 2020 Issued
Array ( [id] => 17615436 [patent_doc_number] => 20220157716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SEMICONDUCTOR CIRCUIT FOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/098014 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098014
Semiconductor circuit for memory device and method of manufacturing the same Nov 12, 2020 Issued
Array ( [id] => 17319227 [patent_doc_number] => 20210408277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Transistor Device Structure [patent_app_type] => utility [patent_app_number] => 17/095981 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095981 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095981
Transistor Device Structure Nov 11, 2020 Abandoned
Array ( [id] => 17319199 [patent_doc_number] => 20210408249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => Semiconductor Device and Method of Forming Thereof [patent_app_type] => utility [patent_app_number] => 17/093345 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093345
Semiconductor device and method of forming thereof Nov 8, 2020 Issued
Array ( [id] => 18331765 [patent_doc_number] => 11637018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Barrier layer for contact structures of semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/081738 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081738
Barrier layer for contact structures of semiconductor devices Oct 26, 2020 Issued
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