Search

Fazli Erdem

Examiner (ID: 9525)

Most Active Art Unit
2826
Art Unit(s)
2812, 2826
Total Applications
1655
Issued Applications
1358
Pending Applications
127
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20383588 [patent_doc_number] => 20250366081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 19/175411 [patent_app_country] => US [patent_app_date] => 2025-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19175411 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/175411
LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF Apr 9, 2025 Pending
Array ( [id] => 20418342 [patent_doc_number] => 12501646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Pi-type trench gate silicon carbide MOSFET device and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 18/950687 [patent_app_country] => US [patent_app_date] => 2024-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 492 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18950687 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/950687
PI-TYPE TRENCH GATE SILICON CARBIDE MOSFET DEVICE AND FABRICATION METHOD THEREOF Nov 17, 2024 Issued
Array ( [id] => 19881310 [patent_doc_number] => 20250113567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => LATERAL HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A LATERAL HIGH VOLTAGE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/897009 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18897009 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/897009
LATERAL HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING A LATERAL HIGH VOLTAGE SEMICONDUCTOR DEVICE Sep 25, 2024 Pending
Array ( [id] => 19590165 [patent_doc_number] => 20240387722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SILICON CARBIDE SPLIT-GATE MOSFETS INTEGRATING HIGH-SPEED FREEWHEELING DIODES AND PREPARATION METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/785583 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 490 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/785583
SILICON CARBIDE SPLIT-GATE MOSFETS INTEGRATING HIGH-SPEED FREEWHEELING DIODES AND PREPARATION METHODS THEREOF Jul 25, 2024 Abandoned
Array ( [id] => 19546767 [patent_doc_number] => 20240363803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/766027 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766027 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766027
LIGHT EMITTING DEVICE AND FABRICATING METHOD THEREOF Jul 7, 2024 Pending
Array ( [id] => 19515944 [patent_doc_number] => 20240347630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/756959 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756959 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756959
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Jun 26, 2024 Pending
Array ( [id] => 19515702 [patent_doc_number] => 20240347388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/754948 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754948 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754948
SEMICONDUCTOR INTEGRATED CIRCUIT Jun 25, 2024 Pending
Array ( [id] => 19484331 [patent_doc_number] => 20240332373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/742974 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10992 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742974 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742974
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD Jun 12, 2024 Pending
Array ( [id] => 19452896 [patent_doc_number] => 20240313026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => METHOD FOR FABRICATING HYBRID BONDED STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/674904 [patent_app_country] => US [patent_app_date] => 2024-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674904 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674904
METHOD FOR FABRICATING HYBRID BONDED STRUCTURE May 25, 2024 Pending
Array ( [id] => 19468372 [patent_doc_number] => 20240322042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SEMICONDUCTOR DEVICE INTEGRATING BACKSIDE POWER GRID AND RELATED INTEGRATED CIRCUIT AND FABRICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/672052 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672052 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672052
SEMICONDUCTOR DEVICE INTEGRATING BACKSIDE POWER GRID AND RELATED INTEGRATED CIRCUIT AND FABRICATION METHOD May 22, 2024 Pending
Array ( [id] => 19335740 [patent_doc_number] => 20240250170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SEMICONDUCTOR DEVICE WITH DOPED REGION BETWEEN GATE AND DRAIN [patent_app_type] => utility [patent_app_number] => 18/625798 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625798
SEMICONDUCTOR DEVICE WITH DOPED REGION BETWEEN GATE AND DRAIN Apr 2, 2024 Pending
Array ( [id] => 19269658 [patent_doc_number] => 20240213363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => VERTICAL FIELD EFFECT TRANSISTOR DEVICE AND METHOD OF FABRICATION [patent_app_type] => utility [patent_app_number] => 18/596271 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596271 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596271
VERTICAL FIELD EFFECT TRANSISTOR DEVICE AND METHOD OF FABRICATION Mar 4, 2024 Pending
Array ( [id] => 19237549 [patent_doc_number] => 20240194744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SHIELDING STRUCTURE FOR ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/421158 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421158
SHIELDING STRUCTURE FOR ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES Feb 27, 2024 Pending
Array ( [id] => 19349444 [patent_doc_number] => 20240258408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => REGROWTH UNIFORMITY IN GAN VERTICAL DEVICES [patent_app_type] => utility [patent_app_number] => 18/587327 [patent_app_country] => US [patent_app_date] => 2024-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/587327
REGROWTH UNIFORMITY IN GAN VERTICAL DEVICES Feb 25, 2024 Pending
Array ( [id] => 19206364 [patent_doc_number] => 20240178263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => DUAL FACING BSI IMAGE SENSORS WITH WAFER LEVEL STACKING [patent_app_type] => utility [patent_app_number] => 18/433120 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433120
DUAL FACING BSI IMAGE SENSORS WITH WAFER LEVEL STACKING Feb 4, 2024 Pending
Array ( [id] => 19206392 [patent_doc_number] => 20240178291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => TRANSISTOR UNIT INCLUDING SHARED GATE STRUCTURE, AND SUB-WORD LINE DRIVER AND SEMICONDUCTOR DEVICE BASED ON THE SAME TRANSISTOR UNIT [patent_app_type] => utility [patent_app_number] => 18/431628 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18431628 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/431628
TRANSISTOR UNIT INCLUDING SHARED GATE STRUCTURE, AND SUB-WORD LINE DRIVER AND SEMICONDUCTOR DEVICE BASED ON THE SAME TRANSISTOR UNIT Feb 1, 2024 Pending
Array ( [id] => 19286027 [patent_doc_number] => 20240222505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DESIGNS FOR SILICON CARBIDE MOSFETs [patent_app_type] => utility [patent_app_number] => 18/412650 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412650 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412650
DESIGNS FOR SILICON CARBIDE MOSFETs Jan 14, 2024 Abandoned
Array ( [id] => 19146517 [patent_doc_number] => 20240145547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application [patent_app_type] => utility [patent_app_number] => 18/409045 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409045 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409045
MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application Jan 9, 2024 Pending
Array ( [id] => 19038401 [patent_doc_number] => 20240088216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => HIGH VOLTAGE SEMICONDUCTOR DEVICE COMPRISING A COMBINED JUNCTION TERMINAL PROTECTION STRUCTURE WITH A FERROELECTRIC MATERIAL [patent_app_type] => utility [patent_app_number] => 18/514976 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514976 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/514976
High voltage semiconductor device comprising a combined junction terminal protection structure with a ferroelectric material Nov 19, 2023 Issued
Array ( [id] => 19038400 [patent_doc_number] => 20240088215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => TRENCH MOSFET DEVICE AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/513576 [patent_app_country] => US [patent_app_date] => 2023-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18513576 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/513576
TRENCH MOSFET DEVICE AND MANUFACTURING METHOD THEREFOR Nov 18, 2023 Abandoned
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