Search

Fazli Erdem

Examiner (ID: 17595, Phone: (571)272-1914 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2812, 2826
Total Applications
1715
Issued Applications
1399
Pending Applications
121
Abandoned Applications
217

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19604688 [patent_doc_number] => 20240395568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, TEMPORARY-FIXING MATERIAL, AND APPLICATION FOR MANUFACTURING SEMICONDUCTOR DEVICE OF TEMPORARY-FIXING MATERIAL [patent_app_type] => utility [patent_app_number] => 18/687298 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18687298 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/687298
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, TEMPORARY-FIXING MATERIAL, AND APPLICATION FOR MANUFACTURING SEMICONDUCTOR DEVICE OF TEMPORARY-FIXING MATERIAL Sep 1, 2022 Pending
Array ( [id] => 18488480 [patent_doc_number] => 20230215828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => LAYOUTS OF DATA PADS ON A SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 17/823638 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823638
Layouts of data pads on a semiconductor die Aug 30, 2022 Issued
Array ( [id] => 18488511 [patent_doc_number] => 20230215859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => LAYOUTS OF DATA PADS ON A SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 17/823678 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823678 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823678
Layouts of data pads on a semiconductor die Aug 30, 2022 Issued
Array ( [id] => 19531767 [patent_doc_number] => 20240355669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/689484 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18689484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/689484
SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS Aug 25, 2022 Pending
Array ( [id] => 18335249 [patent_doc_number] => 20230127197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/892660 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892660
Semiconductor device Aug 21, 2022 Issued
Array ( [id] => 20900408 [patent_doc_number] => 12707688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-11 [patent_title] => Semiconductor structure with roughened sidewall and method of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 17/821165 [patent_app_country] => US [patent_app_date] => 2022-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 1942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821165
SEMICONDUCTOR STRUCTURE WITH ROUGHENED SIDEWALL AND METHOD OF MANUFACTURING THEREOF Aug 19, 2022 Pending
Array ( [id] => 18213159 [patent_doc_number] => 20230059423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => MODULE HAVING ELASTIC WAVE DEVICE [patent_app_type] => utility [patent_app_number] => 17/820760 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/820760
MODULE HAVING ELASTIC WAVE DEVICE Aug 17, 2022 Pending
Array ( [id] => 18713003 [patent_doc_number] => 20230335636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR HAVING ENHANCED HIGH-FREQUENCY PERFORMANCE AND METHODS FOR FABRICATING SAME [patent_app_type] => utility [patent_app_number] => 17/889834 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889834 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889834
METAL-OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR HAVING ENHANCED HIGH-FREQUENCY PERFORMANCE AND METHODS FOR FABRICATING SAME Aug 16, 2022 Pending
Array ( [id] => 18226532 [patent_doc_number] => 20230065526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SPLIT-GATE POWER MOS DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/887573 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887573 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887573
Split-gate power MOS device and manufacturing method thereof Aug 14, 2022 Issued
Array ( [id] => 20191229 [patent_doc_number] => 12402368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/887156 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 2436 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 408 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887156
Semiconductor device and method of manufacturing the same Aug 11, 2022 Issued
Array ( [id] => 18308137 [patent_doc_number] => 20230112037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => Semiconductor Structure and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 17/886321 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886321 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886321
Semiconductor structure and method of forming the same Aug 10, 2022 Issued
Array ( [id] => 18416164 [patent_doc_number] => 11670713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => LDMOS and fabricating method of the same [patent_app_type] => utility [patent_app_number] => 17/884599 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3774 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884599
LDMOS and fabricating method of the same Aug 9, 2022 Issued
Array ( [id] => 18040431 [patent_doc_number] => 20220384648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SEMICONDUCTOR DEVICE WITH DOPED REGION BETWEEN GATE AND DRAIN [patent_app_type] => utility [patent_app_number] => 17/884242 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884242
Semiconductor device with doped region between gate and drain Aug 8, 2022 Issued
Array ( [id] => 18040278 [patent_doc_number] => 20220384495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MULTIPLE DEEP TRENCH ISOLATION (MDTI) STRUCTURE FOR CMOS IMAGE SENSOR [patent_app_type] => utility [patent_app_number] => 17/883660 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883660
Multiple deep trench isolation (MDTI) structure for CMOS image sensor Aug 8, 2022 Issued
Array ( [id] => 19016505 [patent_doc_number] => 11923450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => MOSFET in SiC with self-aligned lateral MOS channel [patent_app_type] => utility [patent_app_number] => 17/817384 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 39 [patent_no_of_words] => 6652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17817384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/817384
MOSFET in SiC with self-aligned lateral MOS channel Aug 3, 2022 Issued
Array ( [id] => 20334444 [patent_doc_number] => 12464740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Semiconductor device and module [patent_app_type] => utility [patent_app_number] => 17/880113 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 10404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880113
Semiconductor device and module Aug 2, 2022 Issued
Array ( [id] => 18008832 [patent_doc_number] => 20220367599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/876733 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876733 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876733
Display device Jul 28, 2022 Issued
Array ( [id] => 18008943 [patent_doc_number] => 20220367710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SIC SUPER JUNCTION TRENCH MOSFET [patent_app_type] => utility [patent_app_number] => 17/874655 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874655
SIC SUPER JUNCTION TRENCH MOSFET Jul 26, 2022 Abandoned
Array ( [id] => 19261036 [patent_doc_number] => 12021103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Method for fabricating hybrid bonded structure [patent_app_type] => utility [patent_app_number] => 17/870865 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 6785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870865 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870865
Method for fabricating hybrid bonded structure Jul 21, 2022 Issued
Array ( [id] => 18226821 [patent_doc_number] => 20230065815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/871231 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871231
Semiconductor device and method for manufacturing the same Jul 21, 2022 Issued
Menu