
Feben Haile
Examiner (ID: 9505, Phone: (571)272-3072 , Office: P/2474 )
| Most Active Art Unit | 2474 |
| Art Unit(s) | 2416, 2616, 2663, OPA, 2474 |
| Total Applications | 534 |
| Issued Applications | 353 |
| Pending Applications | 33 |
| Abandoned Applications | 151 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8029283
[patent_doc_number] => 08143726
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-27
[patent_title] => 'Semiconductor device and method of making semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/544894
[patent_app_country] => US
[patent_app_date] => 2009-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 8223
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/143/08143726.pdf
[firstpage_image] =>[orig_patent_app_number] => 12544894
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/544894 | Semiconductor device and method of making semiconductor device | Aug 19, 2009 | Issued |
Array
(
[id] => 6448428
[patent_doc_number] => 20100038795
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-18
[patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/542540
[patent_app_country] => US
[patent_app_date] => 2009-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 10664
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20100038795.pdf
[firstpage_image] =>[orig_patent_app_number] => 12542540
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/542540 | Method of fabricating semiconductor device and semiconductor device | Aug 16, 2009 | Issued |
Array
(
[id] => 6193133
[patent_doc_number] => 20110024887
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-03
[patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH SILICON VIA BASE AND METHOD OF MANUFACTURE THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/534029
[patent_app_country] => US
[patent_app_date] => 2009-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7026
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20110024887.pdf
[firstpage_image] =>[orig_patent_app_number] => 12534029
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/534029 | Integrated circuit packaging system with through silicon via base and method of manufacture thereof | Jul 30, 2009 | Issued |
Array
(
[id] => 4558198
[patent_doc_number] => 07838417
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-23
[patent_title] => 'Semiconductor package with a chip on a support plate'
[patent_app_type] => utility
[patent_app_number] => 12/512461
[patent_app_country] => US
[patent_app_date] => 2009-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1737
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/838/07838417.pdf
[firstpage_image] =>[orig_patent_app_number] => 12512461
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/512461 | Semiconductor package with a chip on a support plate | Jul 29, 2009 | Issued |
Array
(
[id] => 5552408
[patent_doc_number] => 20090286394
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-19
[patent_title] => 'Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections'
[patent_app_type] => utility
[patent_app_number] => 12/509039
[patent_app_country] => US
[patent_app_date] => 2009-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3550
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0286/20090286394.pdf
[firstpage_image] =>[orig_patent_app_number] => 12509039
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/509039 | Method for forming self-assembled mono-layer liner for Cu/porous low-k interconnections | Jul 23, 2009 | Issued |
Array
(
[id] => 6336947
[patent_doc_number] => 20100019390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, MANUFACTURING METHODS THEREOF, AND STACK PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 12/506720
[patent_app_country] => US
[patent_app_date] => 2009-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6611
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20100019390.pdf
[firstpage_image] =>[orig_patent_app_number] => 12506720
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/506720 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP, MANUFACTURING METHODS THEREOF, AND STACK PACKAGE | Jul 20, 2009 | Abandoned |
Array
(
[id] => 5989411
[patent_doc_number] => 20110012254
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-01-20
[patent_title] => 'Air Cavity Package with Copper Heat Sink and Ceramic Window Frame'
[patent_app_type] => utility
[patent_app_number] => 12/502440
[patent_app_country] => US
[patent_app_date] => 2009-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2440
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20110012254.pdf
[firstpage_image] =>[orig_patent_app_number] => 12502440
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/502440 | Air cavity package with copper heat sink and ceramic window frame | Jul 13, 2009 | Issued |
Array
(
[id] => 5555634
[patent_doc_number] => 20090267211
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-29
[patent_title] => 'WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/498913
[patent_app_country] => US
[patent_app_date] => 2009-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 4002
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20090267211.pdf
[firstpage_image] =>[orig_patent_app_number] => 12498913
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/498913 | Wafer level package and method of fabricating the same | Jul 6, 2009 | Issued |
Array
(
[id] => 6216081
[patent_doc_number] => 20100052137
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-04
[patent_title] => 'ENHANCED WIRE BOND STABILITY ON REACTIVE METAL SURFACES OF A SEMICONDUCTOR DEVICE BY ENCAPSULATION OF THE BOND STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 12/490900
[patent_app_country] => US
[patent_app_date] => 2009-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7155
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0052/20100052137.pdf
[firstpage_image] =>[orig_patent_app_number] => 12490900
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/490900 | ENHANCED WIRE BOND STABILITY ON REACTIVE METAL SURFACES OF A SEMICONDUCTOR DEVICE BY ENCAPSULATION OF THE BOND STRUCTURE | Jun 23, 2009 | Abandoned |
Array
(
[id] => 8687717
[patent_doc_number] => 08387238
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-03-05
[patent_title] => 'Processes and structures for IC fabrication'
[patent_app_type] => utility
[patent_app_number] => 12/484230
[patent_app_country] => US
[patent_app_date] => 2009-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 76
[patent_no_of_words] => 18169
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12484230
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/484230 | Processes and structures for IC fabrication | Jun 13, 2009 | Issued |
Array
(
[id] => 5558311
[patent_doc_number] => 20090269888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-29
[patent_title] => 'CHIP-BASED THERMO-STACK'
[patent_app_type] => utility
[patent_app_number] => 12/483609
[patent_app_country] => US
[patent_app_date] => 2009-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 123
[patent_figures_cnt] => 123
[patent_no_of_words] => 48029
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12483609
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/483609 | Chip-based thermo-stack | Jun 11, 2009 | Issued |
Array
(
[id] => 5473750
[patent_doc_number] => 20090246916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'Chip Package with Pin Stabilization Layer'
[patent_app_type] => utility
[patent_app_number] => 12/479165
[patent_app_country] => US
[patent_app_date] => 2009-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4430
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0246/20090246916.pdf
[firstpage_image] =>[orig_patent_app_number] => 12479165
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/479165 | Chip Package with Pin Stabilization Layer | Jun 4, 2009 | Abandoned |
Array
(
[id] => 5367908
[patent_doc_number] => 20090305467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/473320
[patent_app_country] => US
[patent_app_date] => 2009-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 29306
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0305/20090305467.pdf
[firstpage_image] =>[orig_patent_app_number] => 12473320
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/473320 | Method for manufacturing semiconductor device | May 27, 2009 | Issued |
Array
(
[id] => 5457721
[patent_doc_number] => 20090257873
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-15
[patent_title] => 'Method and apparatus for prediction-based wind turbine control'
[patent_app_type] => utility
[patent_app_number] => 12/386076
[patent_app_country] => US
[patent_app_date] => 2009-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2831
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0257/20090257873.pdf
[firstpage_image] =>[orig_patent_app_number] => 12386076
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/386076 | Method and apparatus for prediction-based wind turbine control | Apr 13, 2009 | Issued |
Array
(
[id] => 8233292
[patent_doc_number] => 08198736
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-12
[patent_title] => 'Reduced susceptibility to electrostatic discharge during 3D semiconductor device bonding and assembly'
[patent_app_type] => utility
[patent_app_number] => 12/421096
[patent_app_country] => US
[patent_app_date] => 2009-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4065
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/198/08198736.pdf
[firstpage_image] =>[orig_patent_app_number] => 12421096
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/421096 | Reduced susceptibility to electrostatic discharge during 3D semiconductor device bonding and assembly | Apr 8, 2009 | Issued |
Array
(
[id] => 8897232
[patent_doc_number] => 08476755
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-02
[patent_title] => 'High frequency ceramic package and fabrication method for the same'
[patent_app_type] => utility
[patent_app_number] => 12/417217
[patent_app_country] => US
[patent_app_date] => 2009-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 57
[patent_no_of_words] => 6170
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12417217
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/417217 | High frequency ceramic package and fabrication method for the same | Apr 1, 2009 | Issued |
Array
(
[id] => 6321472
[patent_doc_number] => 20100244252
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-30
[patent_title] => 'Self Forming Metal Fluoride Barriers for Fluorinated Low-K Dielectrics'
[patent_app_type] => utility
[patent_app_number] => 12/416131
[patent_app_country] => US
[patent_app_date] => 2009-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3342
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0244/20100244252.pdf
[firstpage_image] =>[orig_patent_app_number] => 12416131
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/416131 | Self Forming Metal Fluoride Barriers for Fluorinated Low-K Dielectrics | Mar 30, 2009 | Abandoned |
Array
(
[id] => 5493450
[patent_doc_number] => 20090261478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-22
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/415154
[patent_app_country] => US
[patent_app_date] => 2009-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4651
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0261/20090261478.pdf
[firstpage_image] =>[orig_patent_app_number] => 12415154
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/415154 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Mar 30, 2009 | Abandoned |
Array
(
[id] => 5469951
[patent_doc_number] => 20090243117
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'CONTACT STRUCTURE, A SEMICONDUCTOR DEVICE EMPLOYING THE SAME, AND METHODS OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/412657
[patent_app_country] => US
[patent_app_date] => 2009-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5555
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0243/20090243117.pdf
[firstpage_image] =>[orig_patent_app_number] => 12412657
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/412657 | Contact structure, a semiconductor device employing the same, and methods of manufacturing the same | Mar 26, 2009 | Issued |
Array
(
[id] => 8104965
[patent_doc_number] => 08154133
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-10
[patent_title] => 'Semiconductor device having low dielectric constant film and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/412576
[patent_app_country] => US
[patent_app_date] => 2009-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 6856
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 264
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/154/08154133.pdf
[firstpage_image] =>[orig_patent_app_number] => 12412576
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/412576 | Semiconductor device having low dielectric constant film and manufacturing method thereof | Mar 26, 2009 | Issued |