Search

Feifei Yeung Lopez

Examiner (ID: 14915, Phone: (571)270-1882 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2899, 2826
Total Applications
1323
Issued Applications
1013
Pending Applications
104
Abandoned Applications
227

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17772583 [patent_doc_number] => 11404536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Thin-film transistor structures with gas spacer [patent_app_type] => utility [patent_app_number] => 15/941557 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 12805 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941557 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941557
Thin-film transistor structures with gas spacer Mar 29, 2018 Issued
Array ( [id] => 15519181 [patent_doc_number] => 10566184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-18 [patent_title] => Process of depositing silicon nitride (SiN) film on nitride semiconductor [patent_app_type] => utility [patent_app_number] => 15/941543 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4412 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941543
Process of depositing silicon nitride (SiN) film on nitride semiconductor Mar 29, 2018 Issued
Array ( [id] => 14938925 [patent_doc_number] => 20190305101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => TRANSISTOR DEVICE WITH CHANNEL RECESS STRUCTURE AND METHOD OF PROVIDING SAME [patent_app_type] => utility [patent_app_number] => 15/939081 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939081 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939081
Transistor device with channel recess structure and method of providing same Mar 27, 2018 Issued
Array ( [id] => 13334945 [patent_doc_number] => 20180219010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 15/937093 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15937093 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/937093
Integrated circuit device Mar 26, 2018 Issued
Array ( [id] => 15703907 [patent_doc_number] => 10608141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Light emitting diode chip having electrode pad [patent_app_type] => utility [patent_app_number] => 15/936321 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 45 [patent_no_of_words] => 16189 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15936321 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/936321
Light emitting diode chip having electrode pad Mar 25, 2018 Issued
Array ( [id] => 13785713 [patent_doc_number] => 20190006395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 15/935488 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15935488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/935488
ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY PANEL Mar 25, 2018 Abandoned
Array ( [id] => 15250313 [patent_doc_number] => 10510685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Dishing prevention columns for bipolar junction transistors [patent_app_type] => utility [patent_app_number] => 15/935363 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 8329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15935363 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/935363
Dishing prevention columns for bipolar junction transistors Mar 25, 2018 Issued
Array ( [id] => 13451783 [patent_doc_number] => 20180277434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => PROCESS OF FORMING OHMIC ELECTRODE ON NITRIDE SEMICONDUCTOR MATERIAL [patent_app_type] => utility [patent_app_number] => 15/928901 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15928901 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/928901
PROCESS OF FORMING OHMIC ELECTRODE ON NITRIDE SEMICONDUCTOR MATERIAL Mar 21, 2018 Abandoned
Array ( [id] => 14705491 [patent_doc_number] => 10380496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Quantum computing assemblies [patent_app_type] => utility [patent_app_number] => 15/925594 [patent_app_country] => US [patent_app_date] => 2018-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 41 [patent_no_of_words] => 19995 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15925594 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/925594
Quantum computing assemblies Mar 18, 2018 Issued
Array ( [id] => 16034859 [patent_doc_number] => 10679861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Manufacturing method of a semiconductor device [patent_app_type] => utility [patent_app_number] => 15/921391 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15921391 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/921391
Manufacturing method of a semiconductor device Mar 13, 2018 Issued
Array ( [id] => 15564877 [patent_doc_number] => 20200066850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => INDIUM PHOSPHIDE CRYSTAL SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/607228 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16607228 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/607228
Indium phosphide crystal substrate Feb 22, 2018 Issued
Array ( [id] => 14801025 [patent_doc_number] => 10403522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Chamber for degassing substrates [patent_app_type] => utility [patent_app_number] => 15/899600 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5328 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15899600 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/899600
Chamber for degassing substrates Feb 19, 2018 Issued
Array ( [id] => 13808435 [patent_doc_number] => 10181486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Elevated pocket pixels, imaging devices and systems including the same and method of forming the same [patent_app_type] => utility [patent_app_number] => 15/896686 [patent_app_country] => US [patent_app_date] => 2018-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 5939 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15896686 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/896686
Elevated pocket pixels, imaging devices and systems including the same and method of forming the same Feb 13, 2018 Issued
Array ( [id] => 16372721 [patent_doc_number] => 10804487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Light-emitting device [patent_app_type] => utility [patent_app_number] => 15/890399 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 48 [patent_no_of_words] => 22430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15890399 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/890399
Light-emitting device Feb 6, 2018 Issued
Array ( [id] => 12824248 [patent_doc_number] => 20180166588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => MONOLITHIC INTEGRATION TECHNIQUES FOR FABRICATING PHOTODETECTORS WITH TRANSISTORS ON SAME SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/882953 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882953 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882953
MONOLITHIC INTEGRATION TECHNIQUES FOR FABRICATING PHOTODETECTORS WITH TRANSISTORS ON SAME SUBSTRATE Jan 28, 2018 Abandoned
Array ( [id] => 14267691 [patent_doc_number] => 10283416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Vertical FETS with variable bottom spacer recess [patent_app_type] => utility [patent_app_number] => 15/869761 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 35 [patent_no_of_words] => 6147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15869761 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/869761
Vertical FETS with variable bottom spacer recess Jan 11, 2018 Issued
Array ( [id] => 17745641 [patent_doc_number] => 11393722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Isolation wall stressor structures to improve channel stress and their methods of fabrication [patent_app_type] => utility [patent_app_number] => 16/651116 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 34 [patent_no_of_words] => 12277 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16651116 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/651116
Isolation wall stressor structures to improve channel stress and their methods of fabrication Jan 11, 2018 Issued
Array ( [id] => 15061515 [patent_doc_number] => 10461070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Display apparatus [patent_app_type] => utility [patent_app_number] => 15/865070 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8427 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865070
Display apparatus Jan 7, 2018 Issued
Array ( [id] => 16332407 [patent_doc_number] => 20200303373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => PMOS AND NMOS CONTACTS IN COMMON TRENCH [patent_app_type] => utility [patent_app_number] => 16/649386 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16649386 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/649386
PMOS and NMOS contacts in common trench Dec 27, 2017 Issued
Array ( [id] => 12693247 [patent_doc_number] => 20180122915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => METHOD AND STRUCTURE FOR FORMING MOSFET WITH REDUCED PARASITIC CAPACITANCE [patent_app_type] => utility [patent_app_number] => 15/856309 [patent_app_country] => US [patent_app_date] => 2017-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15856309 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/856309
Method and structure for forming MOSFET with reduced parasitic capacitance Dec 27, 2017 Issued
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