Search

Feifei Yeung Lopez

Examiner (ID: 1896, Phone: (571)270-1882 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2899, 2826
Total Applications
1330
Issued Applications
1017
Pending Applications
106
Abandoned Applications
227

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13667681 [patent_doc_number] => 10164022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => FinFETs with strained well regions [patent_app_type] => utility [patent_app_number] => 15/688214 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/688214
FinFETs with strained well regions Aug 27, 2017 Issued
Array ( [id] => 16394665 [patent_doc_number] => 20200335606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => VERTICAL TUNNELING FIELD-EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/303714 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16303714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/303714
VERTICAL TUNNELING FIELD-EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME Aug 21, 2017 Abandoned
Array ( [id] => 13419995 [patent_doc_number] => 20180261540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 15/679444 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679444
Integrated circuit device Aug 16, 2017 Issued
Array ( [id] => 12223600 [patent_doc_number] => 20180061961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'METHOD FOR MANUFACTURING A BIPOLAR JUNCTION TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/678152 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4347 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678152
Method for manufacturing a bipolar junction transistor Aug 15, 2017 Issued
Array ( [id] => 12849304 [patent_doc_number] => 20180174941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND A CHIP STACK PACKAGE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 15/678197 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678197 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678197
Semiconductor memory device and a chip stack package having the same Aug 15, 2017 Issued
Array ( [id] => 12779272 [patent_doc_number] => 20180151592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => ARRAY SUBSTRATE, METHOD FOR FORMING ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/678868 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678868 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678868
Array substrate, method for forming array substrate, display panel and display device Aug 15, 2017 Issued
Array ( [id] => 12236217 [patent_doc_number] => 20180069080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'LOW-VOLTAGE CHARGE-COUPLED DEVICES WITH A HETEROSTRUCTURE CHARGE-STORAGE WELL' [patent_app_type] => utility [patent_app_number] => 15/679003 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7257 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679003 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679003
Low-voltage charge-coupled devices with a heterostructure charge-storage well Aug 15, 2017 Issued
Array ( [id] => 12693064 [patent_doc_number] => 20180122854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/679084 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679084 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679084
Electronic device and method for fabricating the same Aug 15, 2017 Issued
Array ( [id] => 12779905 [patent_doc_number] => 20180151803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => MASK FOR DEPOSITION, METHOD OF MANUFACTURING MASK, AND METHOD OF MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/677119 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10633 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -39 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677119 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/677119
Mask for deposition, method of manufacturing mask, and method of manufacturing display device Aug 14, 2017 Issued
Array ( [id] => 13242747 [patent_doc_number] => 10134580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-20 [patent_title] => Metallization levels and methods of making thereof [patent_app_type] => utility [patent_app_number] => 15/677693 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3301 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677693 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/677693
Metallization levels and methods of making thereof Aug 14, 2017 Issued
Array ( [id] => 12396072 [patent_doc_number] => 09966278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-08 [patent_title] => Stack packages having with confined underfill fillet and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/677339 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677339 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/677339
Stack packages having with confined underfill fillet and methods of manufacturing the same Aug 14, 2017 Issued
Array ( [id] => 15375851 [patent_doc_number] => 10529653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Electronic components with integral lead frame and wires [patent_app_type] => utility [patent_app_number] => 15/677578 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2456 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677578 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/677578
Electronic components with integral lead frame and wires Aug 14, 2017 Issued
Array ( [id] => 12129272 [patent_doc_number] => 20180012857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'Semiconductor Device and Method of Forming PoP Semiconductor Device with RDL Over Top Package' [patent_app_type] => utility [patent_app_number] => 15/676881 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 27054 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676881 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/676881
Semiconductor device and method of forming PoP semiconductor device with RDL over top package Aug 13, 2017 Issued
Array ( [id] => 12650544 [patent_doc_number] => 20180108679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/675853 [patent_app_country] => US [patent_app_date] => 2017-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675853 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675853
Display device Aug 13, 2017 Issued
Array ( [id] => 12188663 [patent_doc_number] => 20180047599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'PROCESS KIT EROSION AND SERVICE LIFE PREDICTION' [patent_app_type] => utility [patent_app_number] => 15/674180 [patent_app_country] => US [patent_app_date] => 2017-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15674180 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/674180
Process kit erosion and service life prediction Aug 9, 2017 Issued
Array ( [id] => 13936463 [patent_doc_number] => 20190051747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => FULLY DEPLETED SILICON ON INSULATOR (FDSOI) LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR (LDMOS) FOR HIGH FREQUENCY APPLICATIONS [patent_app_type] => utility [patent_app_number] => 15/671590 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/671590
Fully depleted silicon on insulator (FDSOI) lateral double-diffused metal oxide semiconductor (LDMOS) for high frequency applications Aug 7, 2017 Issued
Array ( [id] => 16782012 [patent_doc_number] => 20210119091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/629422 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16629422 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/629422
Method of producing an optoelectronic semiconductor device Aug 3, 2017 Issued
Array ( [id] => 12823519 [patent_doc_number] => 20180166345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/665562 [patent_app_country] => US [patent_app_date] => 2017-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10218 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15665562 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/665562
Semiconductor devices Jul 31, 2017 Issued
Array ( [id] => 12122621 [patent_doc_number] => 20180006207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'LIGHT EMITTING DEVICE, MANUFACTURING METHOD FOR THE LIGHT EMITTING DEVICE, AND LIGHTING MODULE HAVING THE LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/663038 [patent_app_country] => US [patent_app_date] => 2017-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15663038 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/663038
Light emitting device, manufacturing method for the light emitting device, and lighting module having the light emitting device Jul 27, 2017 Issued
Array ( [id] => 14526357 [patent_doc_number] => 10340450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Resistive random access memory structure and forming method thereof [patent_app_type] => utility [patent_app_number] => 15/660295 [patent_app_country] => US [patent_app_date] => 2017-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4998 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15660295 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/660295
Resistive random access memory structure and forming method thereof Jul 25, 2017 Issued
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