Search

Feliciano S. Mejia

Examiner (ID: 8565, Phone: (571)270-5994 , Office: P/2492 )

Most Active Art Unit
2492
Art Unit(s)
2492
Total Applications
268
Issued Applications
216
Pending Applications
3
Abandoned Applications
51

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8474552 [patent_doc_number] => 20120273958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'MULTILAYER INTERCONNECT STRUCTURE AND METHOD FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/096898 [patent_app_country] => US [patent_app_date] => 2011-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13096898 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/096898
Multilayer interconnect structure and method for integrated circuits Apr 27, 2011 Issued
Array ( [id] => 7805384 [patent_doc_number] => 20120056336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'SEMICONDUCTOR PACKAGE FOR CONTROLLING WARPAGE' [patent_app_type] => utility [patent_app_number] => 13/096618 [patent_app_country] => US [patent_app_date] => 2011-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20120056336.pdf [firstpage_image] =>[orig_patent_app_number] => 13096618 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/096618
Semiconductor package for controlling warpage Apr 27, 2011 Issued
Array ( [id] => 7577364 [patent_doc_number] => 20110291246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE WITH STACK CHIP STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/096338 [patent_app_country] => US [patent_app_date] => 2011-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291246.pdf [firstpage_image] =>[orig_patent_app_number] => 13096338 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/096338
Semiconductor chip and semiconductor package with stack chip structure Apr 27, 2011 Issued
Array ( [id] => 9978109 [patent_doc_number] => 09024421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Connection arrangement for semiconductor power modules' [patent_app_type] => utility [patent_app_number] => 13/096155 [patent_app_country] => US [patent_app_date] => 2011-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5863 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13096155 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/096155
Connection arrangement for semiconductor power modules Apr 27, 2011 Issued
Array ( [id] => 8897228 [patent_doc_number] => 08476751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Stacked semiconductor package and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/096143 [patent_app_country] => US [patent_app_date] => 2011-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5074 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13096143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/096143
Stacked semiconductor package and method for manufacturing the same Apr 27, 2011 Issued
Array ( [id] => 6189122 [patent_doc_number] => 20110171809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST' [patent_app_type] => utility [patent_app_number] => 13/070825 [patent_app_country] => US [patent_app_date] => 2011-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7701 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20110171809.pdf [firstpage_image] =>[orig_patent_app_number] => 13070825 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/070825
Method for fabricating high density pillar structures by double patterning using positive photoresist Mar 23, 2011 Issued
Array ( [id] => 5936916 [patent_doc_number] => 20110212568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'Phase change memory devices including phase change layer formed by selective growth methods and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/064410 [patent_app_country] => US [patent_app_date] => 2011-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8156 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20110212568.pdf [firstpage_image] =>[orig_patent_app_number] => 13064410 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/064410
Phase change memory devices including phase change layer formed by selective growth methods and methods of manufacturing the same Mar 22, 2011 Issued
Array ( [id] => 8519664 [patent_doc_number] => 20120319072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'METHOD FOR MANUFACTURING NON-VOLATILE MEMORY DEVICE, NON-VOLATILE MEMORY ELEMENT, AND NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/580401 [patent_app_country] => US [patent_app_date] => 2011-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8671 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13580401 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/580401
Method for manufacturing non-volatile memory device, non-volatile memory element, and non-volatile memory device Feb 22, 2011 Issued
Array ( [id] => 8258079 [patent_doc_number] => 08207571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Non-volatile memory device with a threshold voltage change rate controlled by gate oxide phase' [patent_app_type] => utility [patent_app_number] => 13/032836 [patent_app_country] => US [patent_app_date] => 2011-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2704 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13032836 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/032836
Non-volatile memory device with a threshold voltage change rate controlled by gate oxide phase Feb 22, 2011 Issued
Array ( [id] => 6106186 [patent_doc_number] => 20110187008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTER DEVICE' [patent_app_type] => utility [patent_app_number] => 13/013130 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4329 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20110187008.pdf [firstpage_image] =>[orig_patent_app_number] => 13013130 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/013130
Interconnection tape providing a serial electrode pad connection in a semiconductor device Jan 24, 2011 Issued
Array ( [id] => 8713126 [patent_doc_number] => 08399266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Test structure for detection of gap in conductive layer of multilayer gate stack' [patent_app_type] => utility [patent_app_number] => 13/013133 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3293 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013133 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/013133
Test structure for detection of gap in conductive layer of multilayer gate stack Jan 24, 2011 Issued
Array ( [id] => 8310480 [patent_doc_number] => 20120187505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation' [patent_app_type] => utility [patent_app_number] => 13/013206 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3478 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013206 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/013206
Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation Jan 24, 2011 Abandoned
Array ( [id] => 9496466 [patent_doc_number] => 08735279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Air-dielectric for subtractive etch line and via metallization' [patent_app_type] => utility [patent_app_number] => 13/013108 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4561 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13013108 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/013108
Air-dielectric for subtractive etch line and via metallization Jan 24, 2011 Issued
Array ( [id] => 5955770 [patent_doc_number] => 20110180838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE IN WHICH THE NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING ELEMENT IS MOUNTED IN PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/011592 [patent_app_country] => US [patent_app_date] => 2011-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6615 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20110180838.pdf [firstpage_image] =>[orig_patent_app_number] => 13011592 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/011592
Light emitting element including side surface dielectric layer for avoiding impurity adhesion Jan 20, 2011 Issued
Array ( [id] => 8785164 [patent_doc_number] => 08432009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-30 [patent_title] => 'Method and system for providing magnetic layers having insertion layers for use in spin transfer torque memories' [patent_app_type] => utility [patent_app_number] => 13/011849 [patent_app_country] => US [patent_app_date] => 2011-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 7995 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13011849 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/011849
Method and system for providing magnetic layers having insertion layers for use in spin transfer torque memories Jan 20, 2011 Issued
Array ( [id] => 8483325 [patent_doc_number] => 20120282732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'METHOD FOR FABRICATING A BACK CONTACT SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 13/519249 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3159 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13519249 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/519249
Method for fabricating a back contact solar cell Jan 17, 2011 Issued
Array ( [id] => 8489571 [patent_doc_number] => 20120288978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'METHOD FOR FORMING BUFFER LAYER IN DYE-SENSITIZED SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 13/519913 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4877 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13519913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/519913
Method for forming buffer layer in dye-sensitized solar cell Dec 21, 2010 Issued
Array ( [id] => 8489569 [patent_doc_number] => 20120288977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'METHOD FOR MANUFACTURING DYE-SENSITIZED SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 13/519655 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2974 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13519655 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/519655
METHOD FOR MANUFACTURING DYE-SENSITIZED SOLAR CELL Dec 21, 2010 Abandoned
Array ( [id] => 8489573 [patent_doc_number] => 20120288980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'METHOD FOR MANUFACTURING A BACK CONTACT SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 13/519227 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2778 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13519227 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/519227
Method for manufacturing a back contact solar cell Dec 16, 2010 Issued
Array ( [id] => 8441946 [patent_doc_number] => 20120258562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'METHOD OF PRODUCTION OF CIS-BASED THIN FILM SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 13/515721 [patent_app_country] => US [patent_app_date] => 2010-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6266 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13515721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/515721
Method of production of CIS-based thin film solar cell Dec 13, 2010 Issued
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