Search

Feliciano S. Mejia

Examiner (ID: 8565, Phone: (571)270-5994 , Office: P/2492 )

Most Active Art Unit
2492
Art Unit(s)
2492
Total Applications
268
Issued Applications
216
Pending Applications
3
Abandoned Applications
51

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4582926 [patent_doc_number] => 07834393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Semiconductor device and manufacturing method of the semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/894319 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5829 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/834/07834393.pdf [firstpage_image] =>[orig_patent_app_number] => 11894319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/894319
Semiconductor device and manufacturing method of the semiconductor device Aug 19, 2007 Issued
Array ( [id] => 10178876 [patent_doc_number] => 09209088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-08 [patent_title] => 'Semiconductor devices and methods of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 11/832449 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8139 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11832449 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/832449
Semiconductor devices and methods of manufacture thereof Jul 31, 2007 Issued
Array ( [id] => 5361101 [patent_doc_number] => 20090035895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'CHIP PACKAGE AND CHIP PACKAGING PROCESS THEREOF' [patent_app_type] => utility [patent_app_number] => 11/830188 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2534 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20090035895.pdf [firstpage_image] =>[orig_patent_app_number] => 11830188 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830188
CHIP PACKAGE AND CHIP PACKAGING PROCESS THEREOF Jul 29, 2007 Abandoned
Array ( [id] => 4654872 [patent_doc_number] => 20080023732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'USE OF CARBON CO-IMPLANTATION WITH MILLISECOND ANNEAL TO PRODUCE ULTRA-SHALLOW JUNCTIONS' [patent_app_type] => utility [patent_app_number] => 11/829438 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20080023732.pdf [firstpage_image] =>[orig_patent_app_number] => 11829438 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/829438
USE OF CARBON CO-IMPLANTATION WITH MILLISECOND ANNEAL TO PRODUCE ULTRA-SHALLOW JUNCTIONS Jul 26, 2007 Abandoned
Array ( [id] => 5518591 [patent_doc_number] => 20090026572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Method of Manufacturing a Semiconductor Device, Method of Manufacturing a SOI Device, Semiconductor Device, and SOI Device' [patent_app_type] => utility [patent_app_number] => 11/828268 [patent_app_country] => US [patent_app_date] => 2007-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4358 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20090026572.pdf [firstpage_image] =>[orig_patent_app_number] => 11828268 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/828268
Method of manufacturing a semiconductor device, method of manufacturing a SOI device, semiconductor device, and SOI device Jul 24, 2007 Issued
Array ( [id] => 4906840 [patent_doc_number] => 20080017606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'METHOD OF FORMING STRUCTURE, BANK STRUCTURE, ELECTRONIC CIRCUIT, ELECTRONIC DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/778889 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7105 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20080017606.pdf [firstpage_image] =>[orig_patent_app_number] => 11778889 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/778889
METHOD OF FORMING STRUCTURE, BANK STRUCTURE, ELECTRONIC CIRCUIT, ELECTRONIC DEVICE AND ELECTRONIC APPARATUS Jul 16, 2007 Abandoned
Array ( [id] => 9440777 [patent_doc_number] => 08709887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Method for fabricating a nitrided silicon-oxide gate dielectric' [patent_app_type] => utility [patent_app_number] => 11/778238 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3442 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11778238 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/778238
Method for fabricating a nitrided silicon-oxide gate dielectric Jul 15, 2007 Issued
Array ( [id] => 8398324 [patent_doc_number] => 08268703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-18 [patent_title] => 'Surface roughening process' [patent_app_type] => utility [patent_app_number] => 11/827709 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 4381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11827709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/827709
Surface roughening process Jul 12, 2007 Issued
Array ( [id] => 4909762 [patent_doc_number] => 20080020528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Method of manufacturing semiconductor device and method of manufacturing nonvolatile semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 11/826229 [patent_app_country] => US [patent_app_date] => 2007-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 31722 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20080020528.pdf [firstpage_image] =>[orig_patent_app_number] => 11826229 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/826229
Method of manufacturing a semiconductor device and a non-volatile semiconductor storage device including the formation of an insulating layer using a plasma treatment Jul 12, 2007 Issued
Array ( [id] => 4803073 [patent_doc_number] => 20080014661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'METHOD FOR THE MANUFACTURE OF SOLAR PANELS AND SPECIAL TRANSPORT CARRIER' [patent_app_type] => utility [patent_app_number] => 11/776089 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3064 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20080014661.pdf [firstpage_image] =>[orig_patent_app_number] => 11776089 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/776089
METHOD FOR THE MANUFACTURE OF SOLAR PANELS AND SPECIAL TRANSPORT CARRIER Jul 10, 2007 Abandoned
Array ( [id] => 5016252 [patent_doc_number] => 20070259461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'SEMICONDUCTOR WAFER EXAMINATION METHOD AND SEMICONDUCTOR CHIP MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 11/775449 [patent_app_country] => US [patent_app_date] => 2007-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2720 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20070259461.pdf [firstpage_image] =>[orig_patent_app_number] => 11775449 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775449
SEMICONDUCTOR WAFER EXAMINATION METHOD AND SEMICONDUCTOR CHIP MANUFACTURING METHOD Jul 9, 2007 Abandoned
Array ( [id] => 5310285 [patent_doc_number] => 20090017566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Substrate Removal During LED Formation' [patent_app_type] => utility [patent_app_number] => 11/775059 [patent_app_country] => US [patent_app_date] => 2007-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20090017566.pdf [firstpage_image] =>[orig_patent_app_number] => 11775059 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/775059
Substrate removal during LED formation Jul 8, 2007 Issued
Array ( [id] => 5293776 [patent_doc_number] => 20090008702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'DIELECTRIC CHARGE-TRAPPING MATERIALS HAVING DOPED METAL SITES' [patent_app_type] => utility [patent_app_number] => 11/774298 [patent_app_country] => US [patent_app_date] => 2007-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4403 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20090008702.pdf [firstpage_image] =>[orig_patent_app_number] => 11774298 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774298
Dielectric charge-trapping materials having doped metal sites Jul 5, 2007 Issued
Array ( [id] => 4933091 [patent_doc_number] => 20080003866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'WIRING STRUCTURE IN A SEMICONDUCTOR DEVICE, METHOD OF FORMING THE WIRING STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE WIRING STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/771939 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10624 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003866.pdf [firstpage_image] =>[orig_patent_app_number] => 11771939 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/771939
Wiring structure in a semiconductor device, method of forming the wiring structure, semiconductor device including the wiring structure and method of manufacturing the semiconductor device Jun 28, 2007 Issued
Array ( [id] => 4749227 [patent_doc_number] => 20080157298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Stress Mitigation in Packaged Microchips' [patent_app_type] => utility [patent_app_number] => 11/770369 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3584 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157298.pdf [firstpage_image] =>[orig_patent_app_number] => 11770369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770369
Stress mitigation in packaged microchips Jun 27, 2007 Issued
Array ( [id] => 4749227 [patent_doc_number] => 20080157298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Stress Mitigation in Packaged Microchips' [patent_app_type] => utility [patent_app_number] => 11/770369 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3584 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157298.pdf [firstpage_image] =>[orig_patent_app_number] => 11770369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770369
Stress mitigation in packaged microchips Jun 27, 2007 Issued
Array ( [id] => 4749227 [patent_doc_number] => 20080157298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Stress Mitigation in Packaged Microchips' [patent_app_type] => utility [patent_app_number] => 11/770369 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3584 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157298.pdf [firstpage_image] =>[orig_patent_app_number] => 11770369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770369
Stress mitigation in packaged microchips Jun 27, 2007 Issued
Array ( [id] => 7515826 [patent_doc_number] => 08039898 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device' [patent_app_type] => utility [patent_app_number] => 11/824169 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 5215 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/039/08039898.pdf [firstpage_image] =>[orig_patent_app_number] => 11824169 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/824169
Process for manufacturing a charge-balance power diode and an edge-termination structure for a charge-balance semiconductor power device Jun 27, 2007 Issued
Array ( [id] => 14655 [patent_doc_number] => 07804142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Semiconductor device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/743189 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 55 [patent_no_of_words] => 12912 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/804/07804142.pdf [firstpage_image] =>[orig_patent_app_number] => 11743189 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/743189
Semiconductor device and fabrication method thereof May 1, 2007 Issued
Array ( [id] => 4654825 [patent_doc_number] => 20080023685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'MEMORY DEVICE AND METHOD OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 11/743459 [patent_app_country] => US [patent_app_date] => 2007-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12598 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20080023685.pdf [firstpage_image] =>[orig_patent_app_number] => 11743459 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/743459
MEMORY DEVICE AND METHOD OF MAKING SAME May 1, 2007 Abandoned
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