Fernando L. Toledo

Array ( [id] => 4968477 [patent_doc_number] => 20070108479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'RESISTANCE ELEMENT HAVING REDUCED AREA' [patent_app_type] => utility [patent_app_number] => 11/556427 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5517 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20070108479.pdf [firstpage_image] =>[orig_patent_app_number] => 11556427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5148857 [patent_doc_number] => 20070048917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Process for Producing Semiconductor Integrated Circuit Device' [patent_app_type] => utility [patent_app_number] => 11/553690 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 21947 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20070048917.pdf [firstpage_image] =>[orig_patent_app_number] => 11553690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 311379 [patent_doc_number] => 07528410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/584524 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 14817 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528410.pdf [firstpage_image] =>[orig_patent_app_number] => 11584524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 322560 [patent_doc_number] => 07517792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Semiconductor device having a multilayer interconnection structure, fabrication method thereof, and designing method thereof' [patent_app_type] => utility [patent_app_number] => 11/584645 [patent_app_country] => US [patent_app_date] => 2006-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 40 [patent_no_of_words] => 9778 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/517/07517792.pdf [firstpage_image] =>[orig_patent_app_number] => 11584645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5154442 [patent_doc_number] => 20070037325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'After deposition method of thinning film to reduce pinhole defects' [patent_app_type] => utility [patent_app_number] => 11/581544 [patent_app_country] => US [patent_app_date] => 2006-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4485 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20070037325.pdf [firstpage_image] =>[orig_patent_app_number] => 11581544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4915781 [patent_doc_number] => 20080096381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Atomic layer deposition process for iridium barrier layers' [patent_app_type] => utility [patent_app_number] => 11/581143 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3422 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20080096381.pdf [firstpage_image] =>[orig_patent_app_number] => 11581143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 583622 [patent_doc_number] => 07446014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Nanoelectrochemical cell' [patent_app_type] => utility [patent_app_number] => 11/580623 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446014.pdf [firstpage_image] =>[orig_patent_app_number] => 11580623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 404645 [patent_doc_number] => 07288474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Suspension for filling via holes in silicon and method for making the same' [patent_app_type] => utility [patent_app_number] => 11/544220 [patent_app_country] => US [patent_app_date] => 2006-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3367 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288474.pdf [firstpage_image] =>[orig_patent_app_number] => 11544220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5079720 [patent_doc_number] => 20070122944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Individualized Low Parasitic Power Distribution Lines Deposited Over Active Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 11/539486 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6181 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20070122944.pdf [firstpage_image] =>[orig_patent_app_number] => 11539486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4915731 [patent_doc_number] => 20080096331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'METHOD FOR FABRICATING HIGH COMPRESSIVE STRESS FILM AND STRAINED-SILICON TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 11/538803 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3887 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20080096331.pdf [firstpage_image] =>[orig_patent_app_number] => 11538803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 243267 [patent_doc_number] => 07589001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Semiconductor base and its manufacturing method, and semiconductor crystal manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/541201 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10437 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589001.pdf [firstpage_image] =>[orig_patent_app_number] => 11541201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4944114 [patent_doc_number] => 20080081439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Method of manufacturing semiconductor nanowires' [patent_app_type] => utility [patent_app_number] => 11/540993 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3907 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20080081439.pdf [firstpage_image] =>[orig_patent_app_number] => 11540993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 341580 [patent_doc_number] => 07501338 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-10 [patent_title] => 'Semiconductor package substrate fabrication method' [patent_app_type] => utility [patent_app_number] => 11/527104 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/501/07501338.pdf [firstpage_image] =>[orig_patent_app_number] => 11527104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5313659 [patent_doc_number] => 20090278257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'METHOD TO ASSEMBLE STRUCTURES FROM NANO-MATERIALS' [patent_app_type] => utility [patent_app_number] => 11/525984 [patent_app_country] => US [patent_app_date] => 2006-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20090278257.pdf [firstpage_image] =>[orig_patent_app_number] => 11525984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5205087 [patent_doc_number] => 20070026569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'SEMICONDUCTING DEVICE WITH FOLDED INTERPOSER' [patent_app_type] => utility [patent_app_number] => 11/534274 [patent_app_country] => US [patent_app_date] => 2006-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20070026569.pdf [firstpage_image] =>[orig_patent_app_number] => 11534274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5242387 [patent_doc_number] => 20070020882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'METHOD OF MANUFACTURING TRANSISTOR HAVING RECESSED CHANNEL' [patent_app_type] => utility [patent_app_number] => 11/533273 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5680 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20070020882.pdf [firstpage_image] =>[orig_patent_app_number] => 11533273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 576768 [patent_doc_number] => 07456094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'LDMOS transistor' [patent_app_type] => utility [patent_app_number] => 11/531883 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6412 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/456/07456094.pdf [firstpage_image] =>[orig_patent_app_number] => 11531883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4866939 [patent_doc_number] => 20080145998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'METHOD OF FORMING A LOW-K DUAL DAMASCENE INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/531493 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7286 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20080145998.pdf [firstpage_image] =>[orig_patent_app_number] => 11531493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 582160 [patent_doc_number] => 07449406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same' [patent_app_type] => utility [patent_app_number] => 11/519153 [patent_app_country] => US [patent_app_date] => 2006-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 98 [patent_no_of_words] => 11592 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/449/07449406.pdf [firstpage_image] =>[orig_patent_app_number] => 11519153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5093011 [patent_doc_number] => 20070114620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'PACKAGE AND ELECTRONIC APPARATUS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/530692 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5965 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20070114620.pdf [firstpage_image] =>[orig_patent_app_number] => 11530692 [rel_patent_id] =>[rel_patent_doc_number] =>)