
Fernando L. Toledo
Supervisory Patent Examiner (ID: 9907, Phone: (571)272-1867 , Office: P/2897 )
| Most Active Art Unit | 2823 |
| Art Unit(s) | 2823, 2897, 2895 |
| Total Applications | 748 |
| Issued Applications | 644 |
| Pending Applications | 8 |
| Abandoned Applications | 96 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7398952
[patent_doc_number] => 20040018711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'Methods for fabricating three dimensional integrated circuits'
[patent_app_type] => new
[patent_app_number] => 10/267484
[patent_app_country] => US
[patent_app_date] => 2002-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 9176
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20040018711.pdf
[firstpage_image] =>[orig_patent_app_number] => 10267484
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/267484 | Methods for fabricating three dimensional integrated circuits | Oct 7, 2002 | Abandoned |
Array
(
[id] => 534475
[patent_doc_number] => 07176111
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-13
[patent_title] => 'Method for depositing polycrystalline SiGe suitable for micromachining and devices obtained thereof'
[patent_app_type] => utility
[patent_app_number] => 10/263623
[patent_app_country] => US
[patent_app_date] => 2002-10-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/176/07176111.pdf
[firstpage_image] =>[orig_patent_app_number] => 10263623
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/263623 | Method for depositing polycrystalline SiGe suitable for micromachining and devices obtained thereof | Oct 2, 2002 | Issued |
Array
(
[id] => 6817900
[patent_doc_number] => 20030068858
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-10
[patent_title] => 'Integrated circuit fabrication dual plasma process with separate introduction of different gases into gas flow'
[patent_app_type] => new
[patent_app_number] => 10/260824
[patent_app_country] => US
[patent_app_date] => 2002-09-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0068/20030068858.pdf
[firstpage_image] =>[orig_patent_app_number] => 10260824
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/260824 | Method of forming a metal-insulator-metal capacitor in an interconnect cavity | Sep 26, 2002 | Issued |
Array
(
[id] => 7267827
[patent_doc_number] => 20040056345
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Via interconnect forming process and electronic component product thereof'
[patent_app_type] => new
[patent_app_number] => 10/254703
[patent_app_country] => US
[patent_app_date] => 2002-09-25
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10254703
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/254703 | Via interconnect forming process and electronic component product thereof | Sep 24, 2002 | Issued |
Array
(
[id] => 6713816
[patent_doc_number] => 20030025164
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[patent_kind] => A1
[patent_issue_date] => 2003-02-06
[patent_title] => 'Semiconductor device and fabrication method thereof'
[patent_app_type] => new
[patent_app_number] => 10/252410
[patent_app_country] => US
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[pdf_file] => publications/A1/0025/20030025164.pdf
[firstpage_image] =>[orig_patent_app_number] => 10252410
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/252410 | Semiconductor device and fabrication method thereof | Sep 23, 2002 | Issued |
Array
(
[id] => 662683
[patent_doc_number] => 07101764
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-05
[patent_title] => 'High-voltage transistor and fabrication process'
[patent_app_type] => utility
[patent_app_number] => 10/247073
[patent_app_country] => US
[patent_app_date] => 2002-09-18
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[firstpage_image] =>[orig_patent_app_number] => 10247073
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/247073 | High-voltage transistor and fabrication process | Sep 17, 2002 | Issued |
Array
(
[id] => 672083
[patent_doc_number] => 07091094
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-15
[patent_title] => 'Method of making a semiconductor device having a gate electrode with an hourglass shape'
[patent_app_type] => utility
[patent_app_number] => 10/231094
[patent_app_country] => US
[patent_app_date] => 2002-08-30
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10231094
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/231094 | Method of making a semiconductor device having a gate electrode with an hourglass shape | Aug 29, 2002 | Issued |
Array
(
[id] => 797951
[patent_doc_number] => 07427538
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-23
[patent_title] => 'Semiconductor on insulator apparatus and method'
[patent_app_type] => utility
[patent_app_number] => 10/222173
[patent_app_country] => US
[patent_app_date] => 2002-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/07/427/07427538.pdf
[firstpage_image] =>[orig_patent_app_number] => 10222173
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/222173 | Semiconductor on insulator apparatus and method | Aug 15, 2002 | Issued |
Array
(
[id] => 1107629
[patent_doc_number] => 06808977
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[patent_kind] => B2
[patent_issue_date] => 2004-10-26
[patent_title] => 'Method of manufacturing semiconductor device'
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[patent_app_number] => 10/207234
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/207234 | Method of manufacturing semiconductor device | Jul 29, 2002 | Issued |
Array
(
[id] => 6529759
[patent_doc_number] => 20020192864
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[patent_issue_date] => 2002-12-19
[patent_title] => 'Method of manufacturing integrated circuits'
[patent_app_type] => new
[patent_app_number] => 10/202642
[patent_app_country] => US
[patent_app_date] => 2002-07-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0192/20020192864.pdf
[firstpage_image] =>[orig_patent_app_number] => 10202642
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/202642 | Method of manufacturing integrated circuits | Jul 22, 2002 | Abandoned |
Array
(
[id] => 1082848
[patent_doc_number] => 06833283
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-21
[patent_title] => 'Methods for fabricating polymer light emitting devices by lamination'
[patent_app_type] => B2
[patent_app_number] => 10/196524
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[pdf_file] => patents/06/833/06833283.pdf
[firstpage_image] =>[orig_patent_app_number] => 10196524
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/196524 | Methods for fabricating polymer light emitting devices by lamination | Jul 15, 2002 | Issued |
Array
(
[id] => 1162715
[patent_doc_number] => 06759250
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-06
[patent_title] => 'Deposition method for lead germanate ferroelectric structure with multi-layered electrode'
[patent_app_type] => B2
[patent_app_number] => 10/196503
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[firstpage_image] =>[orig_patent_app_number] => 10196503
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/196503 | Deposition method for lead germanate ferroelectric structure with multi-layered electrode | Jul 14, 2002 | Issued |
Array
(
[id] => 6735665
[patent_doc_number] => 20030013300
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[patent_issue_date] => 2003-01-16
[patent_title] => 'Method and apparatus for depositing tungsten after surface treatment to improve film characteristics'
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[firstpage_image] =>[orig_patent_app_number] => 10196514
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/196514 | Method and apparatus for depositing tungsten after surface treatment to improve film characteristics | Jul 14, 2002 | Issued |
Array
(
[id] => 6742982
[patent_doc_number] => 20030020165
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[patent_title] => 'Semiconductor device, and method for manufacturing the same'
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[pdf_file] => publications/A1/0020/20030020165.pdf
[firstpage_image] =>[orig_patent_app_number] => 10194073
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Array
(
[id] => 7296414
[patent_doc_number] => 20040214363
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[patent_issue_date] => 2004-10-28
[patent_title] => 'ZnSe based light emitting device with In layer'
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Array
(
[id] => 6851623
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[firstpage_image] =>[orig_patent_app_number] => 10184914
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/184914 | Method of manufacturing semiconductor device | Jun 30, 2002 | Issued |
Array
(
[id] => 1050019
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[patent_issue_date] => 2005-03-01
[patent_title] => 'Method for creating thick oxide on the bottom surface of a trench structure in silicon'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/177783 | Method for creating thick oxide on the bottom surface of a trench structure in silicon | Jun 18, 2002 | Issued |
Array
(
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[patent_title] => 'Method for low temperature oxidation of silicon'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/164924 | Method for low temperature oxidation of silicon | Jun 3, 2002 | Abandoned |
Array
(
[id] => 779181
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[patent_title] => 'Thin film transistor and active matrix type display unit production methods therefor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/333194 | Thin film transistor and active matrix type display unit production methods therefor | May 15, 2002 | Issued |
Array
(
[id] => 6723510
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[patent_title] => 'Low-strength plasma treatment for interconnects'
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[pdf_file] => publications/A1/0205/20030205822.pdf
[firstpage_image] =>[orig_patent_app_number] => 10137693
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/137693 | Low-strength plasma treatment for interconnects | May 1, 2002 | Abandoned |