Search

Fernando L. Toledo

Supervisory Patent Examiner (ID: 9907, Phone: (571)272-1867 , Office: P/2897 )

Most Active Art Unit
2823
Art Unit(s)
2823, 2897, 2895
Total Applications
748
Issued Applications
644
Pending Applications
8
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1089176 [patent_doc_number] => 06828226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Removal of SiON residue after CMP' [patent_app_type] => B1 [patent_app_number] => 10/042573 [patent_app_country] => US [patent_app_date] => 2002-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1328 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/828/06828226.pdf [firstpage_image] =>[orig_patent_app_number] => 10042573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042573
Removal of SiON residue after CMP Jan 8, 2002 Issued
Array ( [id] => 6081015 [patent_doc_number] => 20020081773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Light-emitting element, semiconductor light-emitting device, and manufacturing methods therefor' [patent_app_type] => new [patent_app_number] => 10/014454 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 22818 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081773.pdf [firstpage_image] =>[orig_patent_app_number] => 10014454 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/014454
Light-emitting element, semiconductor light-emitting device, and manufacturing methods therefor Dec 13, 2001 Issued
Array ( [id] => 719866 [patent_doc_number] => 07049187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Manufacturing method of polymetal gate electrode' [patent_app_type] => utility [patent_app_number] => 10/468441 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 75 [patent_no_of_words] => 21953 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049187.pdf [firstpage_image] =>[orig_patent_app_number] => 10468441 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/468441
Manufacturing method of polymetal gate electrode Oct 30, 2001 Issued
Array ( [id] => 7445777 [patent_doc_number] => 20040051153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Semiconductor integrated circuit device and process for producing the same' [patent_app_type] => new [patent_app_number] => 10/468462 [patent_app_country] => US [patent_app_date] => 2003-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 20992 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20040051153.pdf [firstpage_image] =>[orig_patent_app_number] => 10468462 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/468462
Semiconductor integrated circuit device and process for producing the same Oct 30, 2001 Issued
Array ( [id] => 1332498 [patent_doc_number] => 06596622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Semiconductor device having a multi-layer pad and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/976114 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 49 [patent_no_of_words] => 6401 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/596/06596622.pdf [firstpage_image] =>[orig_patent_app_number] => 09976114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976114
Semiconductor device having a multi-layer pad and manufacturing method thereof Oct 14, 2001 Issued
Array ( [id] => 654537 [patent_doc_number] => 07109056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Electro-and electroless plating of metal in the manufacture of PCRAM devices' [patent_app_type] => utility [patent_app_number] => 09/956783 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6139 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/109/07109056.pdf [firstpage_image] =>[orig_patent_app_number] => 09956783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956783
Electro-and electroless plating of metal in the manufacture of PCRAM devices Sep 19, 2001 Issued
Array ( [id] => 1130467 [patent_doc_number] => 06787447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Semiconductor processing methods of forming integrated circuitry' [patent_app_type] => B2 [patent_app_number] => 09/952897 [patent_app_country] => US [patent_app_date] => 2001-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1913 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787447.pdf [firstpage_image] =>[orig_patent_app_number] => 09952897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952897
Semiconductor processing methods of forming integrated circuitry Sep 10, 2001 Issued
Array ( [id] => 6778808 [patent_doc_number] => 20030049889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Method of manufacturing multilayer modules' [patent_app_type] => new [patent_app_number] => 09/949203 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7734 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20030049889.pdf [firstpage_image] =>[orig_patent_app_number] => 09949203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/949203
Method of manufacturing multilayer modules Sep 6, 2001 Abandoned
Array ( [id] => 6570695 [patent_doc_number] => 20020084456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Multilayered wiring board and production method thereof' [patent_app_type] => new [patent_app_number] => 09/948964 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9866 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20020084456.pdf [firstpage_image] =>[orig_patent_app_number] => 09948964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948964
Multilayered wiring board and production method thereof Sep 6, 2001 Abandoned
Array ( [id] => 6221884 [patent_doc_number] => 20020003264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Method to form shallow junction transistors while eliminating shorts due to junction spiking' [patent_app_type] => new [patent_app_number] => 09/943307 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5465 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003264.pdf [firstpage_image] =>[orig_patent_app_number] => 09943307 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943307
Method to form shallow junction transistors while eliminating shorts due to junction spiking Aug 30, 2001 Issued
Array ( [id] => 6826922 [patent_doc_number] => 20030177980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Method for reducing semiconductor resistance, device for reducing semiconductor resistance and semiconductor element' [patent_app_type] => new [patent_app_number] => 10/362513 [patent_app_country] => US [patent_app_date] => 2003-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8398 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20030177980.pdf [firstpage_image] =>[orig_patent_app_number] => 10362513 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/362513
Method for reducing semiconductor resistance, device for reducing semiconductor resistance and semiconductor element Aug 21, 2001 Issued
Array ( [id] => 1017975 [patent_doc_number] => 06890869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Low-dielectric silicon nitride film and method of forming the same, semiconductor device and fabrication process thereof' [patent_app_type] => utility [patent_app_number] => 10/333683 [patent_app_country] => US [patent_app_date] => 2001-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 39 [patent_no_of_words] => 9357 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/890/06890869.pdf [firstpage_image] =>[orig_patent_app_number] => 10333683 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/333683
Low-dielectric silicon nitride film and method of forming the same, semiconductor device and fabrication process thereof Aug 18, 2001 Issued
Array ( [id] => 6688507 [patent_doc_number] => 20030032232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Semiconductor transistor having a polysilicon emitter and methods of making the same' [patent_app_type] => new [patent_app_number] => 09/928914 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2122 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20030032232.pdf [firstpage_image] =>[orig_patent_app_number] => 09928914 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928914
Semiconductor transistor having a polysilicon emitter and methods of making the same Aug 12, 2001 Issued
Array ( [id] => 1179868 [patent_doc_number] => 06740549 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Gate structures having sidewall spacers using selective deposition and method of forming the same' [patent_app_type] => B1 [patent_app_number] => 09/927604 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1961 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/740/06740549.pdf [firstpage_image] =>[orig_patent_app_number] => 09927604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927604
Gate structures having sidewall spacers using selective deposition and method of forming the same Aug 9, 2001 Issued
Array ( [id] => 6028893 [patent_doc_number] => 20020017730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 09/924293 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 12198 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20020017730.pdf [firstpage_image] =>[orig_patent_app_number] => 09924293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924293
Semiconductor device Aug 7, 2001 Issued
Array ( [id] => 1002356 [patent_doc_number] => 06908810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation' [patent_app_type] => utility [patent_app_number] => 09/924903 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2673 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/908/06908810.pdf [firstpage_image] =>[orig_patent_app_number] => 09924903 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924903
Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation Aug 7, 2001 Issued
Array ( [id] => 1101701 [patent_doc_number] => 06815314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Hermetic chip and method of manufacture' [patent_app_type] => B2 [patent_app_number] => 09/923687 [patent_app_country] => US [patent_app_date] => 2001-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5195 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815314.pdf [firstpage_image] =>[orig_patent_app_number] => 09923687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923687
Hermetic chip and method of manufacture Aug 5, 2001 Issued
Array ( [id] => 1209195 [patent_doc_number] => 06713319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method for fabricating a semiconductor apparatus including a sealing member with reduced thermal stress' [patent_app_type] => B2 [patent_app_number] => 09/920713 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 6860 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713319.pdf [firstpage_image] =>[orig_patent_app_number] => 09920713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920713
Method for fabricating a semiconductor apparatus including a sealing member with reduced thermal stress Aug 2, 2001 Issued
Array ( [id] => 1155649 [patent_doc_number] => 06764912 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Passivation of nitride spacer' [patent_app_type] => B1 [patent_app_number] => 09/919943 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2047 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764912.pdf [firstpage_image] =>[orig_patent_app_number] => 09919943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919943
Passivation of nitride spacer Aug 1, 2001 Issued
Array ( [id] => 6745343 [patent_doc_number] => 20030022526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Process for fabricating a dielectric film using plasma oxidation' [patent_app_type] => new [patent_app_number] => 09/918853 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9877 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022526.pdf [firstpage_image] =>[orig_patent_app_number] => 09918853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/918853
Process for fabricating a dielectric film using plasma oxidation Jul 29, 2001 Issued
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