Search

Fernando L. Toledo

Supervisory Patent Examiner (ID: 9907, Phone: (571)272-1867 , Office: P/2897 )

Most Active Art Unit
2823
Art Unit(s)
2823, 2897, 2895
Total Applications
748
Issued Applications
644
Pending Applications
8
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6896186 [patent_doc_number] => 20010026976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Method of fabricating a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/818773 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6959 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026976.pdf [firstpage_image] =>[orig_patent_app_number] => 09818773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/818773
Method of fabricating a semiconductor device Mar 27, 2001 Abandoned
Array ( [id] => 1101665 [patent_doc_number] => 06815299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Method for manufacturing silicon carbide device using water rich anneal' [patent_app_type] => B2 [patent_app_number] => 09/817154 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 37 [patent_no_of_words] => 11041 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815299.pdf [firstpage_image] =>[orig_patent_app_number] => 09817154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817154
Method for manufacturing silicon carbide device using water rich anneal Mar 26, 2001 Issued
Array ( [id] => 6881472 [patent_doc_number] => 20010047944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Fixture and method for uniform electroless metal deposition on integrated circuit bond pads' [patent_app_type] => new [patent_app_number] => 09/817694 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3258 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047944.pdf [firstpage_image] =>[orig_patent_app_number] => 09817694 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817694
Fixture and method for uniform electroless metal deposition on integrated circuit bond pads Mar 25, 2001 Abandoned
Array ( [id] => 6895210 [patent_doc_number] => 20010026000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Semiconductor device and a method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/816393 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4054 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026000.pdf [firstpage_image] =>[orig_patent_app_number] => 09816393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/816393
Semiconductor device and a method for manufacturing the same Mar 25, 2001 Abandoned
Array ( [id] => 6474536 [patent_doc_number] => 20020022361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Metal via contact of a semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 09/812564 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3182 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20020022361.pdf [firstpage_image] =>[orig_patent_app_number] => 09812564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812564
Metal via contact of a semiconductor device and method for fabricating the same Mar 20, 2001 Issued
Array ( [id] => 1024492 [patent_doc_number] => 06884653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Folded interposer' [patent_app_type] => utility [patent_app_number] => 09/813724 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4035 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884653.pdf [firstpage_image] =>[orig_patent_app_number] => 09813724 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813724
Folded interposer Mar 20, 2001 Issued
Array ( [id] => 408736 [patent_doc_number] => 07285806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Semiconductor device having an active region formed from group III nitride' [patent_app_type] => utility [patent_app_number] => 09/813304 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 45 [patent_no_of_words] => 10392 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285806.pdf [firstpage_image] =>[orig_patent_app_number] => 09813304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813304
Semiconductor device having an active region formed from group III nitride Mar 20, 2001 Issued
Array ( [id] => 1394221 [patent_doc_number] => 06541346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process' [patent_app_type] => B2 [patent_app_number] => 09/813293 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11151 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541346.pdf [firstpage_image] =>[orig_patent_app_number] => 09813293 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813293
Method and apparatus for a self-aligned heterojunction bipolar transistor using dielectric assisted metal liftoff process Mar 19, 2001 Issued
Array ( [id] => 6539142 [patent_doc_number] => 20020137268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method of forming silicide contacts and device incorporation same' [patent_app_type] => new [patent_app_number] => 09/812373 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4387 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137268.pdf [firstpage_image] =>[orig_patent_app_number] => 09812373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812373
Method of forming silicide contacts and device incorporation same Mar 19, 2001 Abandoned
Array ( [id] => 1209451 [patent_doc_number] => 06713406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method for depositing dielectric materials onto semiconductor substrates by HDP (high density plasma) CVD (chemical vapor deposition) processes without damage to FET active devices' [patent_app_type] => B1 [patent_app_number] => 09/809833 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2316 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713406.pdf [firstpage_image] =>[orig_patent_app_number] => 09809833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809833
Method for depositing dielectric materials onto semiconductor substrates by HDP (high density plasma) CVD (chemical vapor deposition) processes without damage to FET active devices Mar 18, 2001 Issued
Array ( [id] => 1517220 [patent_doc_number] => 06500706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM' [patent_app_type] => B1 [patent_app_number] => 09/809834 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3756 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500706.pdf [firstpage_image] =>[orig_patent_app_number] => 09809834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809834
Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM Mar 18, 2001 Issued
Array ( [id] => 6895218 [patent_doc_number] => 20010026008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Semiconductor device, a semiconductor module loaded with said semiconductor device and a method of manufacturing said semiconductor device' [patent_app_type] => new [patent_app_number] => 09/810403 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14847 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026008.pdf [firstpage_image] =>[orig_patent_app_number] => 09810403 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810403
Semiconductor device, a semiconductor module loaded with said semiconductor device and a method of manufacturing said semiconductor device Mar 18, 2001 Abandoned
Array ( [id] => 6882686 [patent_doc_number] => 20010049158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Methods of making microelectronic assemblies using compressed resilient layer' [patent_app_type] => new [patent_app_number] => 09/811803 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5460 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20010049158.pdf [firstpage_image] =>[orig_patent_app_number] => 09811803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811803
Methods of making microelectronic assemblies using compressed resilient layer Mar 18, 2001 Issued
Array ( [id] => 5874067 [patent_doc_number] => 20020048890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Sidewall spacer based fet alignment technology' [patent_app_type] => new [patent_app_number] => 09/811733 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4531 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048890.pdf [firstpage_image] =>[orig_patent_app_number] => 09811733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811733
Sidewall spacer based fet alignment technology Mar 18, 2001 Issued
Array ( [id] => 1517341 [patent_doc_number] => 06500749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method to improve copper via electromigration (EM) resistance' [patent_app_type] => B1 [patent_app_number] => 09/810123 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1406 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500749.pdf [firstpage_image] =>[orig_patent_app_number] => 09810123 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810123
Method to improve copper via electromigration (EM) resistance Mar 18, 2001 Issued
Array ( [id] => 5873984 [patent_doc_number] => 20020048828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/809923 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4874 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048828.pdf [firstpage_image] =>[orig_patent_app_number] => 09809923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809923
Semiconductor device with under-fill material below a surface of a semiconductor chip Mar 15, 2001 Issued
Array ( [id] => 7634795 [patent_doc_number] => 06656823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Semiconductor device with schottky contact and method for forming the same' [patent_app_type] => B2 [patent_app_number] => 09/809163 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4400 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656823.pdf [firstpage_image] =>[orig_patent_app_number] => 09809163 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809163
Semiconductor device with schottky contact and method for forming the same Mar 15, 2001 Issued
Array ( [id] => 6898572 [patent_doc_number] => 20010046737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Semiconductor memory device and fabricating method thereof' [patent_app_type] => new [patent_app_number] => 09/808983 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6768 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046737.pdf [firstpage_image] =>[orig_patent_app_number] => 09808983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/808983
Semiconductor memory device and fabricating method thereof Mar 15, 2001 Issued
Array ( [id] => 7612829 [patent_doc_number] => 06903006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Interlayer dielectric film, and method for forming the same and interconnection' [patent_app_type] => utility [patent_app_number] => 09/809043 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7304 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903006.pdf [firstpage_image] =>[orig_patent_app_number] => 09809043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809043
Interlayer dielectric film, and method for forming the same and interconnection Mar 15, 2001 Issued
Array ( [id] => 7093138 [patent_doc_number] => 20010034092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'CMOS sense structure having silicon dioxide outer ring around sense region' [patent_app_type] => new [patent_app_number] => 09/811073 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1862 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034092.pdf [firstpage_image] =>[orig_patent_app_number] => 09811073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811073
CMOS sense structure having silicon dioxide outer ring around sense region Mar 15, 2001 Abandoned
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