Search

Fernando N. Hidalgo

Examiner (ID: 12957, Phone: (571)270-3306 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1613
Issued Applications
1483
Pending Applications
81
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19773114 [patent_doc_number] => 20250054540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => LIFETIME MIXED LEVEL NON-VOLATILE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/926560 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3796 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/926560
Lifetime mixed level non-volatile memory system Oct 24, 2024 Issued
Array ( [id] => 19820708 [patent_doc_number] => 20250078915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => LOW POWER READ CIRCUIT FOR MULTI-BANK MEMORY [patent_app_type] => utility [patent_app_number] => 18/815830 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815830 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815830
LOW POWER READ CIRCUIT FOR MULTI-BANK MEMORY Aug 25, 2024 Pending
Array ( [id] => 19604908 [patent_doc_number] => 20240395788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/793349 [patent_app_country] => US [patent_app_date] => 2024-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11926 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18793349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/793349
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE Aug 1, 2024 Pending
Array ( [id] => 19714619 [patent_doc_number] => 20250024761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => RANDOM NUMBER GENERATION BASED ON THRESHOLD VOLTAGE RANDOMNESS [patent_app_type] => utility [patent_app_number] => 18/782436 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18782436 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/782436
RANDOM NUMBER GENERATION BASED ON THRESHOLD VOLTAGE RANDOMNESS Jul 23, 2024 Pending
Array ( [id] => 19912377 [patent_doc_number] => 12288595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => System and method for providing compression attached memory module compression connectors [patent_app_type] => utility [patent_app_number] => 18/775312 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5998 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775312 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775312
System and method for providing compression attached memory module compression connectors Jul 16, 2024 Issued
Array ( [id] => 19546154 [patent_doc_number] => 20240363190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/771393 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771393 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771393
ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES Jul 11, 2024 Pending
Array ( [id] => 19548520 [patent_doc_number] => 20240365556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => COMPUTE-IN-MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/769532 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769532
COMPUTE-IN-MEMORY DEVICE AND METHOD Jul 10, 2024 Pending
Array ( [id] => 20088559 [patent_doc_number] => 20250218495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY (COP) STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/767238 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767238
MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY (COP) STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME Jul 8, 2024 Pending
Array ( [id] => 19712350 [patent_doc_number] => 20250022492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => POWER CONTROL CHAIN [patent_app_type] => utility [patent_app_number] => 18/766414 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766414 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766414
POWER CONTROL CHAIN Jul 7, 2024 Pending
Array ( [id] => 20167611 [patent_doc_number] => 20250259658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => POWER SUPPLY CIRCUIT, SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/749616 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749616 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749616
POWER SUPPLY CIRCUIT, SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE Jun 20, 2024 Pending
Array ( [id] => 19712707 [patent_doc_number] => 20250022849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => VERTICALLY INTEGRATED MEMORY SYSTEM AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/749416 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11326 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749416 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749416
VERTICALLY INTEGRATED MEMORY SYSTEM AND ASSOCIATED SYSTEMS AND METHODS Jun 19, 2024 Pending
Array ( [id] => 19483724 [patent_doc_number] => 20240331766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => SRAM Design with Four-Poly-Pitch [patent_app_type] => utility [patent_app_number] => 18/744280 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744280 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744280
SRAM design with four-poly-pitch Jun 13, 2024 Issued
Array ( [id] => 20175716 [patent_doc_number] => 12394469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => DRAM computation circuit and method [patent_app_type] => utility [patent_app_number] => 18/743950 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743950
DRAM computation circuit and method Jun 13, 2024 Issued
Array ( [id] => 20409751 [patent_doc_number] => 20250378860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-11 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 18/739767 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739767
MEMORY CIRCUIT AND METHOD OF OPERATING SAME Jun 10, 2024 Pending
Array ( [id] => 19618918 [patent_doc_number] => 20240404598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => 3D CELL AND ARRAY STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/735147 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18735147 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/735147
3D CELL AND ARRAY STRUCTURES Jun 4, 2024 Pending
Array ( [id] => 19646240 [patent_doc_number] => 20240420760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/669285 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669285 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669285
MEMORY DEVICE May 19, 2024 Pending
Array ( [id] => 19420773 [patent_doc_number] => 20240296897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => TECHNIQUES FOR DETERMINING AN INTERFACE CONNECTION STATUS [patent_app_type] => utility [patent_app_number] => 18/660002 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660002 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660002
Techniques for determining an interface connection status May 8, 2024 Issued
Array ( [id] => 19406873 [patent_doc_number] => 20240290384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => ACCESS COMMAND DELAY USING COMMAND DELAY CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/658559 [patent_app_country] => US [patent_app_date] => 2024-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18658559 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/658559
ACCESS COMMAND DELAY USING COMMAND DELAY CIRCUITRY May 7, 2024 Pending
Array ( [id] => 19406861 [patent_doc_number] => 20240290372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 18/657640 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657640
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD May 6, 2024 Abandoned
Array ( [id] => 19394798 [patent_doc_number] => 20240284668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/653241 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653241 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653241
Memory system May 1, 2024 Issued
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