Search

Fernando N. Hidalgo

Examiner (ID: 12957, Phone: (571)270-3306 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1613
Issued Applications
1483
Pending Applications
81
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19007482 [patent_doc_number] => 20240071553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/894528 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894528
Adaptive error avoidance in the memory devices Aug 23, 2022 Issued
Array ( [id] => 19679088 [patent_doc_number] => 12190959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Erase suspend with configurable forward progress [patent_app_type] => utility [patent_app_number] => 17/893755 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893755
Erase suspend with configurable forward progress Aug 22, 2022 Issued
Array ( [id] => 18766745 [patent_doc_number] => 11817152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Generating embedded data in memory cells in a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/892721 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892721 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892721
Generating embedded data in memory cells in a memory sub-system Aug 21, 2022 Issued
Array ( [id] => 19437899 [patent_doc_number] => 20240306397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => EMBEDDED SEMICONDUCTOR RANDOM ACCESS MEMORY STRUCTURE AND CONTROL METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/279569 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18279569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/279569
Embedded semiconductor random access memory structure and control method therefor Aug 11, 2022 Issued
Array ( [id] => 20455744 [patent_doc_number] => 12518804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Memory and read circuit thereof [patent_app_type] => utility [patent_app_number] => 18/575275 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2400 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18575275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/575275
Memory and read circuit thereof Aug 10, 2022 Issued
Array ( [id] => 19401300 [patent_doc_number] => 12075714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Random number generation based on threshold voltage randomness [patent_app_type] => utility [patent_app_number] => 17/818617 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 17098 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818617
Random number generation based on threshold voltage randomness Aug 8, 2022 Issued
Array ( [id] => 19045215 [patent_doc_number] => 11934326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Memory with improved command/address bus utilization [patent_app_type] => utility [patent_app_number] => 17/882550 [patent_app_country] => US [patent_app_date] => 2022-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882550 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/882550
Memory with improved command/address bus utilization Aug 5, 2022 Issued
Array ( [id] => 18958663 [patent_doc_number] => 20240046990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => MEMORY DEVICE WITH FAST WRITE MODE TO MITIGATE POWER LOSS [patent_app_type] => utility [patent_app_number] => 17/817288 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17817288 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/817288
Memory device with fast write mode to mitigate power loss Aug 2, 2022 Issued
Array ( [id] => 18688147 [patent_doc_number] => 11783890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Semiconductor device including distributed write driving arrangement [patent_app_type] => utility [patent_app_number] => 17/816048 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/816048
Semiconductor device including distributed write driving arrangement Jul 28, 2022 Issued
Array ( [id] => 19061709 [patent_doc_number] => 11940944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Fuse recipe update mechanism [patent_app_type] => utility [patent_app_number] => 17/877531 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877531 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877531
Fuse recipe update mechanism Jul 28, 2022 Issued
Array ( [id] => 19582363 [patent_doc_number] => 12148489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Early detection of programming failure for non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/874014 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 13828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874014
Early detection of programming failure for non-volatile memory Jul 25, 2022 Issued
Array ( [id] => 18639266 [patent_doc_number] => 11763882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Low voltage memory device [patent_app_type] => utility [patent_app_number] => 17/814700 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 8070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814700
Low voltage memory device Jul 24, 2022 Issued
Array ( [id] => 18926796 [patent_doc_number] => 20240029800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => TECHNIQUES FOR THRESHOLD VOLTAGE SCANS [patent_app_type] => utility [patent_app_number] => 17/871234 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871234 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871234
Techniques for threshold voltage scans Jul 21, 2022 Issued
Array ( [id] => 18008185 [patent_doc_number] => 20220366952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => Memory Array Staircase Structure [patent_app_type] => utility [patent_app_number] => 17/814341 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814341 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814341
Memory array staircase structure Jul 21, 2022 Issued
Array ( [id] => 17992948 [patent_doc_number] => 20220358985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => USING SPLIT WORD LINES AND SWITCHES FOR REDUCING CAPACITIVE LOADING ON A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/868982 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868982
Using split word lines and switches for reducing capacitive loading on a memory system Jul 19, 2022 Issued
Array ( [id] => 17984717 [patent_doc_number] => 20220350754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => COMPRESSION ATTACHED MEMORY MODULE FOR OFFSET STACKING [patent_app_type] => utility [patent_app_number] => 17/866759 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866759
Compression attached memory module for offset stacking Jul 17, 2022 Issued
Array ( [id] => 17985733 [patent_doc_number] => 20220351770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => METHODS AND APPARATUS FOR DYNAMICALLY ADJUSTING PERFORMANCE OF PARTITIONED MEMORY [patent_app_type] => utility [patent_app_number] => 17/867124 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867124
METHODS AND APPARATUS FOR DYNAMICALLY ADJUSTING PERFORMANCE OF PARTITIONED MEMORY Jul 17, 2022 Pending
Array ( [id] => 17984716 [patent_doc_number] => 20220350753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => SYSTEM AND METHOD FOR PROVIDING COMPRESSION ATTACHED MEMORY MODULE OFFSET STACKING [patent_app_type] => utility [patent_app_number] => 17/866737 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866737
System and method for providing compression attached memory module offset stacking Jul 17, 2022 Issued
Array ( [id] => 17985736 [patent_doc_number] => 20220351773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => Write Assist for a Memory Device and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 17/865453 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/865453
Write assist for a memory device and methods of forming the same Jul 14, 2022 Issued
Array ( [id] => 18161245 [patent_doc_number] => 20230027837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => 3-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/812375 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -65 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/812375
3-dimensional memory string array of thin-film ferroelectric transistors Jul 12, 2022 Issued
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