Search

Fernando N. Hidalgo

Examiner (ID: 12957, Phone: (571)270-3306 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1613
Issued Applications
1483
Pending Applications
81
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17984353 [patent_doc_number] => 20220350390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => OPTIMIZING POWER IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/748704 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748704
Optimizing power in a memory device May 18, 2022 Issued
Array ( [id] => 17839500 [patent_doc_number] => 20220276805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => SYSTEMS AND METHODS FOR ADAPTIVE READ TRAINING OF THREE DIMENSIONAL MEMORY [patent_app_type] => utility [patent_app_number] => 17/749000 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749000
Systems and methods for adaptive read training of three dimensional memory May 18, 2022 Issued
Array ( [id] => 18998915 [patent_doc_number] => 11915769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Non-volatile memory with isolation latch shared between data latch groups [patent_app_type] => utility [patent_app_number] => 17/745120 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 14974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745120
Non-volatile memory with isolation latch shared between data latch groups May 15, 2022 Issued
Array ( [id] => 18540584 [patent_doc_number] => 20230245694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => MEMORY CIRCUIT AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 17/744428 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744428
Memory circuit and method of operating same May 12, 2022 Issued
Array ( [id] => 18774003 [patent_doc_number] => 20230368833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => POWER-EFFICIENT ACCESS LINE OPERATION FOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/662741 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662741
Power-efficient access line operation for memory May 9, 2022 Issued
Array ( [id] => 19487092 [patent_doc_number] => 12106816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Latch performance detection method, device and electronic device [patent_app_type] => utility [patent_app_number] => 17/790472 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7668 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17790472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/790472
Latch performance detection method, device and electronic device May 8, 2022 Issued
Array ( [id] => 17811423 [patent_doc_number] => 20220263258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SYSTEM AND METHOD FOR STACKING COMPRESSION DUAL IN-LINE MEMORY MODULE SCALABILITY [patent_app_type] => utility [patent_app_number] => 17/739540 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739540
System and method for stacking compression dual in-line memory module scalability May 8, 2022 Issued
Array ( [id] => 17809506 [patent_doc_number] => 20220261341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SELF-SEEDED RANDOMIZER FOR DATA RANDOMIZATION IN FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 17/739578 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739578
Self-seeded randomizer for data randomization in flash memory May 8, 2022 Issued
Array ( [id] => 18652792 [patent_doc_number] => 20230298632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/737294 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737294
Semiconductor device May 4, 2022 Issued
Array ( [id] => 18112643 [patent_doc_number] => 20230005523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => CONTROL CIRCUIT, METHOD FOR READING AND WRITING AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/737109 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737109
Control circuit, method for reading and writing and memory May 4, 2022 Issued
Array ( [id] => 18998916 [patent_doc_number] => 11915770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Method of reducing reliability degradation of nonvolatile memory device, nonvolatile memory device using the same and method of testing nonvolatile memory device using the same [patent_app_type] => utility [patent_app_number] => 17/736395 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 15239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736395
Method of reducing reliability degradation of nonvolatile memory device, nonvolatile memory device using the same and method of testing nonvolatile memory device using the same May 3, 2022 Issued
Array ( [id] => 17795322 [patent_doc_number] => 20220254414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => PROGRAMMING ANALOG NEURAL MEMORY CELLS IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/734807 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734807
Programming analog neural memory cells in deep learning artificial neural network May 1, 2022 Issued
Array ( [id] => 17932958 [patent_doc_number] => 20220328084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => STORAGE ELEMENT AND STORAGE APPARATUS [patent_app_type] => utility [patent_app_number] => 17/732911 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732911 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732911
Storage element and storage apparatus Apr 28, 2022 Issued
Array ( [id] => 18743089 [patent_doc_number] => 20230352077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => DISTRIBUTED GLOBAL AND LOCAL REFERENCE VOLTAGE GENERATION [patent_app_type] => utility [patent_app_number] => 17/730333 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730333 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730333
Distributed global and local reference voltage generation Apr 26, 2022 Issued
Array ( [id] => 18520622 [patent_doc_number] => 11710516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Double data rate (DDR) memory controller apparatus and method [patent_app_type] => utility [patent_app_number] => 17/728673 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728673
Double data rate (DDR) memory controller apparatus and method Apr 24, 2022 Issued
Array ( [id] => 20345797 [patent_doc_number] => 12469532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Systems for near-sensor analogue computing for ultrafast responsive tactile sensing [patent_app_type] => utility [patent_app_number] => 18/285937 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 52 [patent_no_of_words] => 1974 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18285937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/285937
Systems for near-sensor analogue computing for ultrafast responsive tactile sensing Apr 21, 2022 Issued
Array ( [id] => 18379457 [patent_doc_number] => 20230154546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => PAGE BUFFER CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS INCLUDING PAGE BUFFER CIRCUIT, AND OPERATING METHOD OF SEMICONDUCTOR MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/726986 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726986
Page buffer circuit, semiconductor memory apparatus including page buffer circuit, and operating method of semiconductor memory apparatus Apr 21, 2022 Issued
Array ( [id] => 18967210 [patent_doc_number] => 11900988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Electronic device related to a precharge operation [patent_app_type] => utility [patent_app_number] => 17/726847 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726847 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726847
Electronic device related to a precharge operation Apr 21, 2022 Issued
Array ( [id] => 17780280 [patent_doc_number] => 20220246630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/725638 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725638
Memory system Apr 20, 2022 Issued
Array ( [id] => 19371681 [patent_doc_number] => 12063786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Compute-in-memory device and method [patent_app_type] => utility [patent_app_number] => 17/726086 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726086 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726086
Compute-in-memory device and method Apr 20, 2022 Issued
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