
Fernando N. Hidalgo
Examiner (ID: 12957, Phone: (571)270-3306 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 1613 |
| Issued Applications | 1483 |
| Pending Applications | 81 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19046480
[patent_doc_number] => 11935599
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-19
[patent_title] => Burst programming of a NAND flash cell
[patent_app_type] => utility
[patent_app_number] => 17/725911
[patent_app_country] => US
[patent_app_date] => 2022-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 19528
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725911
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/725911 | Burst programming of a NAND flash cell | Apr 20, 2022 | Issued |
Array
(
[id] => 18713545
[patent_doc_number] => 20230336181
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-19
[patent_title] => DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL STACKED MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/723692
[patent_app_country] => US
[patent_app_date] => 2022-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7461
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723692
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/723692 | Divided quad clock-based inter-die clocking in a three-dimensional stacked memory device | Apr 18, 2022 | Issued |
Array
(
[id] => 18644570
[patent_doc_number] => 11768637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-26
[patent_title] => Interface circuit and system including same
[patent_app_type] => utility
[patent_app_number] => 17/721497
[patent_app_country] => US
[patent_app_date] => 2022-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 8853
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721497
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/721497 | Interface circuit and system including same | Apr 14, 2022 | Issued |
Array
(
[id] => 17899095
[patent_doc_number] => 20220308757
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => CONFIGURABLE LINK INTERFACES FOR A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/721160
[patent_app_country] => US
[patent_app_date] => 2022-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721160
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/721160 | Configurable link interfaces for a memory device | Apr 13, 2022 | Issued |
Array
(
[id] => 17932960
[patent_doc_number] => 20220328086
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => FRONT END BUFFER HAVING FERROELECTRIC FIELD EFFECT TRANSISTOR (FeFET) BASED MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/719637
[patent_app_country] => US
[patent_app_date] => 2022-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7866
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17719637
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/719637 | Front end buffer having ferroelectric field effect transistor (FeFET) based memory | Apr 12, 2022 | Issued |
Array
(
[id] => 19414513
[patent_doc_number] => 12080347
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-09-03
[patent_title] => Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement
[patent_app_type] => utility
[patent_app_number] => 17/710835
[patent_app_country] => US
[patent_app_date] => 2022-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 21156
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710835
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/710835 | Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement | Mar 30, 2022 | Issued |
Array
(
[id] => 20215965
[patent_doc_number] => 12412619
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-09
[patent_title] => Apparatuses and methods for row decoder with multiple section enable signal voltage domains
[patent_app_type] => utility
[patent_app_number] => 17/709753
[patent_app_country] => US
[patent_app_date] => 2022-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709753
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/709753 | Apparatuses and methods for row decoder with multiple section enable signal voltage domains | Mar 30, 2022 | Issued |
Array
(
[id] => 18679526
[patent_doc_number] => 20230317182
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => DYNAMIC PROGRAM CACHING
[patent_app_type] => utility
[patent_app_number] => 17/710978
[patent_app_country] => US
[patent_app_date] => 2022-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10581
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710978
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/710978 | Dynamic program caching | Mar 30, 2022 | Issued |
Array
(
[id] => 18827500
[patent_doc_number] => 11842789
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-12
[patent_title] => Capacitor string structure, memory device and electronic device
[patent_app_type] => utility
[patent_app_number] => 17/709174
[patent_app_country] => US
[patent_app_date] => 2022-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 4335
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17709174
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/709174 | Capacitor string structure, memory device and electronic device | Mar 29, 2022 | Issued |
Array
(
[id] => 17932954
[patent_doc_number] => 20220328080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => METHOD FOR WRITING TO AND READING OUT A NON-VOLATILE ELECTRONIC MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/708163
[patent_app_country] => US
[patent_app_date] => 2022-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5358
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708163
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/708163 | Method for writing to and reading out a non-volatile electronic memory | Mar 29, 2022 | Issued |
Array
(
[id] => 19244336
[patent_doc_number] => 12014787
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-18
[patent_title] => Techniques for determining an interface connection status
[patent_app_type] => utility
[patent_app_number] => 17/657063
[patent_app_country] => US
[patent_app_date] => 2022-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 16206
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657063
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/657063 | Techniques for determining an interface connection status | Mar 28, 2022 | Issued |
Array
(
[id] => 18682404
[patent_doc_number] => 20230320081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => SEMICONDUCTOR DEVICE HAVING DIODE CONNECTEDTO MEMORY DEVICE AND CIRCUIT INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/706789
[patent_app_country] => US
[patent_app_date] => 2022-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8686
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706789
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/706789 | Semiconductor device having diode connectedto memory device and circuit including the same | Mar 28, 2022 | Issued |
Array
(
[id] => 18661029
[patent_doc_number] => 20230307042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => MULTIPLE TRANSISTOR ARCHITECTURE FOR THREE-DIMENSIONAL MEMORY ARRAYS
[patent_app_type] => utility
[patent_app_number] => 17/701463
[patent_app_country] => US
[patent_app_date] => 2022-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12694
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701463
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/701463 | Multiple transistor architecture for three-dimensional memory arrays | Mar 21, 2022 | Issued |
Array
(
[id] => 18935239
[patent_doc_number] => 11887677
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-30
[patent_title] => Quick pass write programming techniques in a memory device
[patent_app_type] => utility
[patent_app_number] => 17/701365
[patent_app_country] => US
[patent_app_date] => 2022-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 31
[patent_no_of_words] => 16177
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701365
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/701365 | Quick pass write programming techniques in a memory device | Mar 21, 2022 | Issued |
Array
(
[id] => 18653323
[patent_doc_number] => 20230299163
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => INVERTERS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 17/655479
[patent_app_country] => US
[patent_app_date] => 2022-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9067
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655479
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/655479 | Inverters, and related memory devices and electronic systems | Mar 17, 2022 | Issued |
Array
(
[id] => 20276415
[patent_doc_number] => 12446204
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => SRAM with P-type access transistors and complementary field-effect transistor technology
[patent_app_type] => utility
[patent_app_number] => 17/686241
[patent_app_country] => US
[patent_app_date] => 2022-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 30
[patent_no_of_words] => 7848
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686241
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/686241 | SRAM with P-type access transistors and complementary field-effect transistor technology | Mar 2, 2022 | Issued |
Array
(
[id] => 18147387
[patent_doc_number] => 20230021244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/681662
[patent_app_country] => US
[patent_app_date] => 2022-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22740
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17681662
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/681662 | Semiconductor memory device | Feb 24, 2022 | Issued |
Array
(
[id] => 17660443
[patent_doc_number] => 20220180908
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => MEMORY DEVICE WITH SELECTIVE PRECHARGING
[patent_app_type] => utility
[patent_app_number] => 17/676544
[patent_app_country] => US
[patent_app_date] => 2022-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8213
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676544
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/676544 | Memory device with selective precharging | Feb 20, 2022 | Issued |
Array
(
[id] => 18226427
[patent_doc_number] => 20230065421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => EXPRESS PROGRAMMING USING ADVANCED CACHE REGISTER RELEASE IN A MEMORY SUB-SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/675526
[patent_app_country] => US
[patent_app_date] => 2022-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13955
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675526
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/675526 | Express programming using advanced cache register release in a memory sub-system | Feb 17, 2022 | Issued |
Array
(
[id] => 18890797
[patent_doc_number] => 11869574
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Semiconductor memory device and memory system including the same
[patent_app_type] => utility
[patent_app_number] => 17/674908
[patent_app_country] => US
[patent_app_date] => 2022-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 28
[patent_no_of_words] => 12452
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674908
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/674908 | Semiconductor memory device and memory system including the same | Feb 17, 2022 | Issued |