
Fernando N. Hidalgo
Examiner (ID: 12957, Phone: (571)270-3306 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 1613 |
| Issued Applications | 1483 |
| Pending Applications | 81 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18475530
[patent_doc_number] => 20230209818
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
[patent_app_type] => utility
[patent_app_number] => 17/674478
[patent_app_country] => US
[patent_app_date] => 2022-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4946
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674478
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/674478 | Methods used in forming a memory array comprising strings of memory cells | Feb 16, 2022 | Issued |
Array
(
[id] => 18669705
[patent_doc_number] => 11776615
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-03
[patent_title] => Sequential SLC read optimization
[patent_app_type] => utility
[patent_app_number] => 17/673302
[patent_app_country] => US
[patent_app_date] => 2022-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 7684
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673302
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/673302 | Sequential SLC read optimization | Feb 15, 2022 | Issued |
Array
(
[id] => 18493326
[patent_doc_number] => 11698742
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Garbage collection in a memory component using an adjusted parameter
[patent_app_type] => utility
[patent_app_number] => 17/673408
[patent_app_country] => US
[patent_app_date] => 2022-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7535
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673408
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/673408 | Garbage collection in a memory component using an adjusted parameter | Feb 15, 2022 | Issued |
Array
(
[id] => 19062911
[patent_doc_number] => 11942156
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-26
[patent_title] => Memory device related to performing a program operation on memory cells
[patent_app_type] => utility
[patent_app_number] => 17/671906
[patent_app_country] => US
[patent_app_date] => 2022-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 33
[patent_no_of_words] => 11346
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671906
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/671906 | Memory device related to performing a program operation on memory cells | Feb 14, 2022 | Issued |
Array
(
[id] => 18143330
[patent_doc_number] => 20230017178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-19
[patent_title] => APPARATUS AND METHOD FOR ERASING DATA IN A NON-VOLATILE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/671002
[patent_app_country] => US
[patent_app_date] => 2022-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671002
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/671002 | Apparatus and method for erasing data in a non-volatile memory device | Feb 13, 2022 | Issued |
Array
(
[id] => 17628591
[patent_doc_number] => 20220163606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-26
[patent_title] => SPIN ELEMENT AND MAGNETIC MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/668742
[patent_app_country] => US
[patent_app_date] => 2022-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8285
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668742
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/668742 | Spin element and magnetic memory | Feb 9, 2022 | Issued |
Array
(
[id] => 19137830
[patent_doc_number] => 11972801
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-30
[patent_title] => Program voltage dependent program source levels
[patent_app_type] => utility
[patent_app_number] => 17/665824
[patent_app_country] => US
[patent_app_date] => 2022-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 25
[patent_no_of_words] => 11391
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17665824
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/665824 | Program voltage dependent program source levels | Feb 6, 2022 | Issued |
Array
(
[id] => 19244317
[patent_doc_number] => 12014768
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-18
[patent_title] => DRAM computation circuit and method
[patent_app_type] => utility
[patent_app_number] => 17/589729
[patent_app_country] => US
[patent_app_date] => 2022-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 11746
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589729
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/589729 | DRAM computation circuit and method | Jan 30, 2022 | Issued |
Array
(
[id] => 19183584
[patent_doc_number] => 11990180
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-21
[patent_title] => Memory device
[patent_app_type] => utility
[patent_app_number] => 17/587075
[patent_app_country] => US
[patent_app_date] => 2022-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7408
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587075
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/587075 | Memory device | Jan 27, 2022 | Issued |
Array
(
[id] => 19062899
[patent_doc_number] => 11942144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-26
[patent_title] => In-memory computation system with drift compensation circuit
[patent_app_type] => utility
[patent_app_number] => 17/582675
[patent_app_country] => US
[patent_app_date] => 2022-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 7817
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582675
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/582675 | In-memory computation system with drift compensation circuit | Jan 23, 2022 | Issued |
Array
(
[id] => 18225357
[patent_doc_number] => 20230064351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => DATA OUTPUT CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/578156
[patent_app_country] => US
[patent_app_date] => 2022-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7705
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578156
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/578156 | Data output control circuit and semiconductor apparatus including the same | Jan 17, 2022 | Issued |
Array
(
[id] => 17691876
[patent_doc_number] => 20220199169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => NOISE REDUCTION DURING PARALLEL PLANE ACCESS IN A MULTI-PLANE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/572057
[patent_app_country] => US
[patent_app_date] => 2022-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10813
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572057
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/572057 | Noise reduction during parallel plane access in a multi-plane memory device | Jan 9, 2022 | Issued |
Array
(
[id] => 18593432
[patent_doc_number] => 11742344
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-29
[patent_title] => Devices including control logic structures, and related methods
[patent_app_type] => utility
[patent_app_number] => 17/647138
[patent_app_country] => US
[patent_app_date] => 2022-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 43
[patent_no_of_words] => 23658
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647138
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/647138 | Devices including control logic structures, and related methods | Jan 4, 2022 | Issued |
Array
(
[id] => 18950762
[patent_doc_number] => 11894065
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-06
[patent_title] => Three-dimensional memory device
[patent_app_type] => utility
[patent_app_number] => 17/569424
[patent_app_country] => US
[patent_app_date] => 2022-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 4958
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569424
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/569424 | Three-dimensional memory device | Jan 4, 2022 | Issued |
Array
(
[id] => 18796712
[patent_doc_number] => 11830538
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-28
[patent_title] => Apparatuses, systems, and methods for data timing alignment in stacked memory
[patent_app_type] => utility
[patent_app_number] => 17/563863
[patent_app_country] => US
[patent_app_date] => 2021-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 12681
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563863
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/563863 | Apparatuses, systems, and methods for data timing alignment in stacked memory | Dec 27, 2021 | Issued |
Array
(
[id] => 18472697
[patent_doc_number] => 20230206985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR READ CLOCK TIMING ALIGNMENT IN STACKED MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/563878
[patent_app_country] => US
[patent_app_date] => 2021-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10352
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563878
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/563878 | Apparatuses, systems, and methods for read clock timing alignment in stacked memory devices | Dec 27, 2021 | Issued |
Array
(
[id] => 17550043
[patent_doc_number] => 20220121385
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-21
[patent_title] => MANAGEMENT OF ERASE SUSPEND AND RESUME OPERATIONS IN MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/562329
[patent_app_country] => US
[patent_app_date] => 2021-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8329
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562329
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/562329 | Management of erase suspend and resume operations in memory devices | Dec 26, 2021 | Issued |
Array
(
[id] => 17536795
[patent_doc_number] => 20220115404
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/561471
[patent_app_country] => US
[patent_app_date] => 2021-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11015
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561471
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/561471 | Semiconductor memory device and method of operating the semiconductor memory device | Dec 22, 2021 | Issued |
Array
(
[id] => 17956151
[patent_doc_number] => 11482264
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-25
[patent_title] => Memory module adapted to implementing computing functions
[patent_app_type] => utility
[patent_app_number] => 17/645527
[patent_app_country] => US
[patent_app_date] => 2021-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 9497
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17645527
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/645527 | Memory module adapted to implementing computing functions | Dec 21, 2021 | Issued |
Array
(
[id] => 18400769
[patent_doc_number] => 11662905
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-30
[patent_title] => Memory system performance enhancements using measured signal and noise characteristics of memory cells
[patent_app_type] => utility
[patent_app_number] => 17/552179
[patent_app_country] => US
[patent_app_date] => 2021-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 9303
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552179
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/552179 | Memory system performance enhancements using measured signal and noise characteristics of memory cells | Dec 14, 2021 | Issued |