Search

Fernando N. Hidalgo

Examiner (ID: 18896, Phone: (571)270-3306 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1640
Issued Applications
1494
Pending Applications
92
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17764533 [patent_doc_number] => 20220238146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => HIGH BANDWIDTH MEMORY SYSTEM USING MULTILEVEL SIGNALING [patent_app_type] => utility [patent_app_number] => 17/483010 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6418 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483010 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483010
High bandwidth memory system using multilevel signaling Sep 22, 2021 Issued
Array ( [id] => 17337988 [patent_doc_number] => 20220004319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => SELECTIVELY OPERABLE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/479802 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479802
Selectively operable memory device Sep 19, 2021 Issued
Array ( [id] => 17941468 [patent_doc_number] => 11475927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Static random-access memory and electronic device [patent_app_type] => utility [patent_app_number] => 17/479940 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479940 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479940
Static random-access memory and electronic device Sep 19, 2021 Issued
Array ( [id] => 20566004 [patent_doc_number] => 12568628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/024823 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 73 [patent_no_of_words] => 25994 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18024823 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/024823
Semiconductor device Sep 15, 2021 Issued
Array ( [id] => 18874464 [patent_doc_number] => 11862285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Sense amplifier, memory and control method of sense amplifier [patent_app_type] => utility [patent_app_number] => 17/474166 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 9244 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474166 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474166
Sense amplifier, memory and control method of sense amplifier Sep 13, 2021 Issued
Array ( [id] => 18112678 [patent_doc_number] => 20230005558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SIGNAL GENERATION CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/447424 [patent_app_country] => US [patent_app_date] => 2021-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447424 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447424
Signal generation circuit and method, and semiconductor memory Sep 10, 2021 Issued
Array ( [id] => 18097033 [patent_doc_number] => 20220415374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => ELECTRONIC DEVICE FOR PERFORMING DATA ALIGNMENT OPERATION [patent_app_type] => utility [patent_app_number] => 17/472411 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12529 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472411
Electronic device for performing data alignment operation Sep 9, 2021 Issued
Array ( [id] => 17615114 [patent_doc_number] => 20220157394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/471168 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471168
Memory device for improving weak-program or stuck bit Sep 9, 2021 Issued
Array ( [id] => 18874408 [patent_doc_number] => 11862229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Reading and writing method of memory device and memory device [patent_app_type] => utility [patent_app_number] => 17/470879 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3932 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470879
Reading and writing method of memory device and memory device Sep 8, 2021 Issued
Array ( [id] => 17463412 [patent_doc_number] => 20220076718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SELF-CORRECTING MODULAR-REDUNDANCY-MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/466015 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/466015
Self-correcting modular-redundancy-memory device Sep 2, 2021 Issued
Array ( [id] => 18804106 [patent_doc_number] => 11837269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Deck-level signal development cascodes [patent_app_type] => utility [patent_app_number] => 17/462213 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 25302 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462213
Deck-level signal development cascodes Aug 30, 2021 Issued
Array ( [id] => 18874405 [patent_doc_number] => 11862226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Systems and methods for pre-read scan of memory devices [patent_app_type] => utility [patent_app_number] => 17/463152 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463152
Systems and methods for pre-read scan of memory devices Aug 30, 2021 Issued
Array ( [id] => 18131115 [patent_doc_number] => 11557330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-17 [patent_title] => Deck-level shuntung in a memory device [patent_app_type] => utility [patent_app_number] => 17/462217 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 19059 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462217
Deck-level shuntung in a memory device Aug 30, 2021 Issued
Array ( [id] => 18228429 [patent_doc_number] => 20230067423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MEMORY SYSTEMS WITH VERTICAL INTEGRATION [patent_app_type] => utility [patent_app_number] => 17/461332 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461332 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461332
Memory systems with vertical integration Aug 29, 2021 Issued
Array ( [id] => 18137097 [patent_doc_number] => 11562785 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-24 [patent_title] => Microelectronic devices, and related memory devices and electronic systems [patent_app_type] => utility [patent_app_number] => 17/446340 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14041 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446340
Microelectronic devices, and related memory devices and electronic systems Aug 29, 2021 Issued
Array ( [id] => 18386008 [patent_doc_number] => 11656789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Asymmetric read sense [patent_app_type] => utility [patent_app_number] => 17/412158 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412158 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412158
Asymmetric read sense Aug 24, 2021 Issued
Array ( [id] => 18080738 [patent_doc_number] => 20220406350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => Memory Array Test Structure and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 17/397414 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/397414
Memory array test structure and method of forming the same Aug 8, 2021 Issued
Array ( [id] => 17645022 [patent_doc_number] => 20220172761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => STORAGE CIRCUIT PROVIDED WITH VARIABLE RESISTANCE TYPE ELEMENTS, AND ITS TEST DEVICE [patent_app_type] => utility [patent_app_number] => 17/395210 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395210
Storage circuit provided with variable resistance type elements, and its test device Aug 4, 2021 Issued
Array ( [id] => 17941496 [patent_doc_number] => 11475955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Multi-chip package with reduced calibration time and ZQ calibration method thereof [patent_app_type] => utility [patent_app_number] => 17/393784 [patent_app_country] => US [patent_app_date] => 2021-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13428 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393784
Multi-chip package with reduced calibration time and ZQ calibration method thereof Aug 3, 2021 Issued
Array ( [id] => 18796724 [patent_doc_number] => 11830550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Memory with FRAM and SRAM of IC [patent_app_type] => utility [patent_app_number] => 17/392830 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392830
Memory with FRAM and SRAM of IC Aug 2, 2021 Issued
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