Fernando N. Hidalgo

Array ( [id] => 17294210 [patent_doc_number] => 20210390049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => MEMORY MODULES AND METHODS OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 17/157323 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17499482 [patent_doc_number] => 11288188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Dynamic metadata relocation in memory [patent_app_type] => utility [patent_app_number] => 17/154345 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13298 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17340130 [patent_doc_number] => 20220006461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => DELAY CIRCUIT OF DELAY-LOCKED LOOP CIRCUIT AND DELAY-LOCKED LOOP CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/149039 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16934575 [patent_doc_number] => 20210200464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => MEMORY DEVICE INTERFACE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/136728 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17683246 [patent_doc_number] => 11367507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Memory device and electronic device [patent_app_type] => utility [patent_app_number] => 17/135043 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16781410 [patent_doc_number] => 20210118489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => PERFORMING A REFRESH OPERATION BASED ON SYSTEM CHARACTERISTICS [patent_app_type] => utility [patent_app_number] => 17/247801 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18276897 [patent_doc_number] => 11615843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Controlling voltage resistance through metal-oxide device [patent_app_type] => utility [patent_app_number] => 17/124648 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18190764 [patent_doc_number] => 11581368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Memory device, integrated circuit device and method [patent_app_type] => utility [patent_app_number] => 17/122708 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 12949 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17757966 [patent_doc_number] => 11398264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Methods and apparatus for dynamically adjusting performance of partitioned memory [patent_app_type] => utility [patent_app_number] => 17/121466 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 18046 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17424067 [patent_doc_number] => 11257528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Memory device with selective precharging [patent_app_type] => utility [patent_app_number] => 17/113316 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16781947 [patent_doc_number] => 20210119026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => CHARGE STORAGE AND SENSING DEVICES AND METHODS [patent_app_type] => utility [patent_app_number] => 17/111428 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16934573 [patent_doc_number] => 20210200462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => Multi-Array RAM Architecture [patent_app_type] => utility [patent_app_number] => 17/091002 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17091002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16795838 [patent_doc_number] => 20210125655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => FULL BIAS SENSING IN A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/091580 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17091580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16660373 [patent_doc_number] => 20210057010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => STORAGE ELEMENT AND STORAGE APPARATUS [patent_app_type] => utility [patent_app_number] => 17/090321 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17339182 [patent_doc_number] => 20220005513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => DATA STROBE CLOCK OUTPUT CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/089450 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17439036 [patent_doc_number] => 11264377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Devices including control logic structures, and related methods [patent_app_type] => utility [patent_app_number] => 17/089374 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 43 [patent_no_of_words] => 23632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17582605 [patent_doc_number] => 20220139460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => GENERATING EMBEDDED DATA IN MEMORY CELLS IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/086964 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7665 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17803066 [patent_doc_number] => 11417375 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Discharge current mitigation in a memory array [patent_app_type] => utility [patent_app_number] => 17/085154 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 16120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17389079 [patent_doc_number] => 20220036931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => Memory Array Staircase Structure [patent_app_type] => utility [patent_app_number] => 17/081380 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081380 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16624600 [patent_doc_number] => 20210043253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => MEMORY COMPUTATION CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 17/077401 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077401 [rel_patent_id] =>[rel_patent_doc_number] =>)