Search

Fernando N. Hidalgo

Examiner (ID: 543, Phone: (571)270-3306 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1664
Issued Applications
1514
Pending Applications
94
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10501455 [patent_doc_number] => 09229856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Optimized configurable NAND parameters' [patent_app_type] => utility [patent_app_number] => 14/452749 [patent_app_country] => US [patent_app_date] => 2014-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 7545 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14452749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/452749
Optimized configurable NAND parameters Aug 5, 2014 Issued
Array ( [id] => 12214676 [patent_doc_number] => 09911491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Determining a resistance state of a cell in a crossbar memory array' [patent_app_type] => utility [patent_app_number] => 15/324792 [patent_app_country] => US [patent_app_date] => 2014-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4237 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15324792 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/324792
Determining a resistance state of a cell in a crossbar memory array Jul 30, 2014 Issued
Array ( [id] => 10603850 [patent_doc_number] => 09324419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Multiple pass programming for memory with different program pulse widths' [patent_app_type] => utility [patent_app_number] => 14/331784 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 69 [patent_no_of_words] => 22918 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331784 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/331784
Multiple pass programming for memory with different program pulse widths Jul 14, 2014 Issued
Array ( [id] => 10624193 [patent_doc_number] => 09343141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Reprogramming memory with single program pulse per data state' [patent_app_type] => utility [patent_app_number] => 14/331800 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 69 [patent_no_of_words] => 22929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14331800 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/331800
Reprogramming memory with single program pulse per data state Jul 14, 2014 Issued
Array ( [id] => 10666756 [patent_doc_number] => 20160012901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'THREE DIMENSIONAL MEMORY DEVICE AND DATA ERASE METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/330106 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14330106 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/330106
Three dimensional memory device and data erase method thereof Jul 13, 2014 Issued
Array ( [id] => 10990921 [patent_doc_number] => 20160187865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'PLC SYSTEM AND ARITHMETIC-EXPRESSION-DATA-CREATION SUPPORTING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/906175 [patent_app_country] => US [patent_app_date] => 2014-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13989 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14906175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/906175
PLC system and arithmetic-expression-data-creation supporting apparatus Jul 13, 2014 Issued
Array ( [id] => 11221361 [patent_doc_number] => 09449702 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-20 [patent_title] => 'Power management' [patent_app_type] => utility [patent_app_number] => 14/326142 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9587 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14326142 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/326142
Power management Jul 7, 2014 Issued
Array ( [id] => 10556846 [patent_doc_number] => 09281048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Semiconductor memory device capable of preventing negative bias temperature instability (NBTI) using self refresh information' [patent_app_type] => utility [patent_app_number] => 14/325852 [patent_app_country] => US [patent_app_date] => 2014-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14325852 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/325852
Semiconductor memory device capable of preventing negative bias temperature instability (NBTI) using self refresh information Jul 7, 2014 Issued
Array ( [id] => 10277064 [patent_doc_number] => 20150162061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'MULTI-CYCLE WRITE LEVELING' [patent_app_type] => utility [patent_app_number] => 14/325140 [patent_app_country] => US [patent_app_date] => 2014-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14325140 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/325140
Multi-cycle write leveling Jul 6, 2014 Issued
Array ( [id] => 10659602 [patent_doc_number] => 20160005746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'MEMORY ARCHITECTURE OF 3D ARRAY WITH INTERLEAVED CONTROL STRUCTURES' [patent_app_type] => utility [patent_app_number] => 14/324892 [patent_app_country] => US [patent_app_date] => 2014-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14324892 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/324892
Memory architecture of 3D array with interleaved control structures Jul 6, 2014 Issued
Array ( [id] => 10590374 [patent_doc_number] => 09311994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 14/324110 [patent_app_country] => US [patent_app_date] => 2014-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 10254 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14324110 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/324110
Non-volatile memory device Jul 3, 2014 Issued
Array ( [id] => 9894338 [patent_doc_number] => 20150049537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/322814 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14322814 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/322814
Electronic device and method for fabricating the same Jul 1, 2014 Issued
Array ( [id] => 10213280 [patent_doc_number] => 20150098272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'PROGRAMMABLE PEAK-CURRENT CONTROL IN NON-VOLATILE MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 14/322102 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5254 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14322102 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/322102
Programmable peak-current control in non-volatile memory devices Jul 1, 2014 Issued
Array ( [id] => 10343343 [patent_doc_number] => 20150228348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/322662 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7031 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14322662 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/322662
Semiconductor device and operating method thereof Jul 1, 2014 Issued
Array ( [id] => 10563275 [patent_doc_number] => 09286956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Memory device, memory module including the memory device, method of fabricating the memory module, and method of repairing the memory module' [patent_app_type] => utility [patent_app_number] => 14/320796 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 8087 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320796 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320796
Memory device, memory module including the memory device, method of fabricating the memory module, and method of repairing the memory module Jun 30, 2014 Issued
Array ( [id] => 10336375 [patent_doc_number] => 20150221380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/321532 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6486 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321532 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321532
Semiconductor device Jun 30, 2014 Issued
Array ( [id] => 11630627 [patent_doc_number] => 20170140817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'MEMRISTIVE MEMORY CELL RESISTANCE SWITCH MONITORING' [patent_app_type] => utility [patent_app_number] => 15/311594 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3403 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15311594 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/311594
Memristive memory cell resistance switch monitoring Jun 19, 2014 Issued
Array ( [id] => 10884054 [patent_doc_number] => 08908443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-09 [patent_title] => 'Storage device and method for performing a self-refresh operation' [patent_app_type] => utility [patent_app_number] => 14/287988 [patent_app_country] => US [patent_app_date] => 2014-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5232 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14287988 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/287988
Storage device and method for performing a self-refresh operation May 26, 2014 Issued
Array ( [id] => 9924655 [patent_doc_number] => 08982629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Method and apparatus for program and erase of select gate transistors' [patent_app_type] => utility [patent_app_number] => 14/285866 [patent_app_country] => US [patent_app_date] => 2014-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 47 [patent_no_of_words] => 23235 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14285866 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/285866
Method and apparatus for program and erase of select gate transistors May 22, 2014 Issued
Array ( [id] => 10189454 [patent_doc_number] => 09218880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Partial update in a ternary content addressable memory' [patent_app_type] => utility [patent_app_number] => 14/282298 [patent_app_country] => US [patent_app_date] => 2014-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8212 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14282298 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/282298
Partial update in a ternary content addressable memory May 19, 2014 Issued
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