
Fernando N. Hidalgo
Examiner (ID: 8782, Phone: (571)270-3306 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 1666 |
| Issued Applications | 1514 |
| Pending Applications | 96 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5197896
[patent_doc_number] => 20070297214
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-27
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/806738
[patent_app_country] => US
[patent_app_date] => 2007-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 10100
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0297/20070297214.pdf
[firstpage_image] =>[orig_patent_app_number] => 11806738
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/806738 | Semiconductor device | Jun 3, 2007 | Abandoned |
Array
(
[id] => 8632901
[patent_doc_number] => 08365000
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-29
[patent_title] => 'Computer system and control method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/755294
[patent_app_country] => US
[patent_app_date] => 2007-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3913
[patent_no_of_claims] => 15
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11755294
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/755294 | Computer system and control method thereof | May 29, 2007 | Issued |
Array
(
[id] => 4789756
[patent_doc_number] => 20080290729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-27
[patent_title] => 'ETHERNET INTERCONNECTION APPARATUS AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 11/752971
[patent_app_country] => US
[patent_app_date] => 2007-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 7545
[patent_no_of_claims] => 60
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0290/20080290729.pdf
[firstpage_image] =>[orig_patent_app_number] => 11752971
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/752971 | ETHERNET INTERCONNECTION APPARATUS AND METHOD | May 23, 2007 | Abandoned |
Array
(
[id] => 214024
[patent_doc_number] => RE040990
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2009-11-17
[patent_title] => 'Data transmission across asynchronous time domains using phase-shifted data packet'
[patent_app_type] => reissue
[patent_app_number] => 11/805866
[patent_app_country] => US
[patent_app_date] => 2007-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3120
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/040/RE040990.pdf
[firstpage_image] =>[orig_patent_app_number] => 11805866
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/805866 | Data transmission across asynchronous time domains using phase-shifted data packet | May 22, 2007 | Issued |
Array
(
[id] => 7803745
[patent_doc_number] => 08132029
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-06
[patent_title] => 'Method for managing the power transmitted from a central network component to a decentralized network component via a line'
[patent_app_type] => utility
[patent_app_number] => 12/309528
[patent_app_country] => US
[patent_app_date] => 2007-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2669
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[pdf_file] => patents/08/132/08132029.pdf
[firstpage_image] =>[orig_patent_app_number] => 12309528
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/309528 | Method for managing the power transmitted from a central network component to a decentralized network component via a line | May 20, 2007 | Issued |
Array
(
[id] => 5260656
[patent_doc_number] => 20070214289
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-13
[patent_title] => 'DYNAMIC POWER CONTROL FOR REDUCED VOLTAGE LEVEL OF GRAPHICS CONTROLLER COMPONENT OF MEMORY CONTROLLER BASED ON ITS DEGREE OF IDELENESS'
[patent_app_type] => utility
[patent_app_number] => 11/747392
[patent_app_country] => US
[patent_app_date] => 2007-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2751
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[pdf_file] => publications/A1/0214/20070214289.pdf
[firstpage_image] =>[orig_patent_app_number] => 11747392
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/747392 | Dynamic power control for reduced voltage level of graphics controller component of memory controller based on its degree of idleness | May 10, 2007 | Issued |
Array
(
[id] => 4961811
[patent_doc_number] => 20080276236
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-06
[patent_title] => 'DATA PROCESSING DEVICE WITH LOW-POWER CACHE ACCESS MODE'
[patent_app_type] => utility
[patent_app_number] => 11/743388
[patent_app_country] => US
[patent_app_date] => 2007-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4504
[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0276/20080276236.pdf
[firstpage_image] =>[orig_patent_app_number] => 11743388
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/743388 | Data processing device with low-power cache access mode | May 1, 2007 | Issued |
Array
(
[id] => 4961601
[patent_doc_number] => 20080276026
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-06
[patent_title] => 'SELECTIVE DEACTIVATION OF PROCESSOR CORES IN MULTIPLE PROCESSOR CORE SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 11/743341
[patent_app_country] => US
[patent_app_date] => 2007-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 5059
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[pdf_file] => publications/A1/0276/20080276026.pdf
[firstpage_image] =>[orig_patent_app_number] => 11743341
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/743341 | Selective deactivation of processor cores in multiple processor core systems | May 1, 2007 | Issued |
Array
(
[id] => 4961683
[patent_doc_number] => 20080276108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-06
[patent_title] => 'METHOD AND SYSTEM FOR IMPLEMENTING GENERALIZED SYSTEM STUTTER'
[patent_app_type] => utility
[patent_app_number] => 11/743099
[patent_app_country] => US
[patent_app_date] => 2007-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => publications/A1/0276/20080276108.pdf
[firstpage_image] =>[orig_patent_app_number] => 11743099
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/743099 | Method and system for implementing generalized system stutter | Apr 30, 2007 | Issued |
Array
(
[id] => 8816722
[patent_doc_number] => 20130117766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-09
[patent_title] => 'Fabric-Backplane Enterprise Servers with Pluggable I/O Sub-System'
[patent_app_type] => utility
[patent_app_number] => 11/736355
[patent_app_country] => US
[patent_app_date] => 2007-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 61
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/736355 | Fabric-backplane enterprise servers with pluggable I/O sub-system | Apr 16, 2007 | Issued |
Array
(
[id] => 4665594
[patent_doc_number] => 20080256501
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[patent_kind] => A1
[patent_issue_date] => 2008-10-16
[patent_title] => 'System and Method for Updating a Time-Related State of a Migrating Logical Partition'
[patent_app_type] => utility
[patent_app_number] => 11/735750
[patent_app_country] => US
[patent_app_date] => 2007-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => publications/A1/0256/20080256501.pdf
[firstpage_image] =>[orig_patent_app_number] => 11735750
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/735750 | System and method for updating a time-related state of a migrating logical partition | Apr 15, 2007 | Issued |
Array
(
[id] => 4590065
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[patent_issue_date] => 2010-11-09
[patent_title] => 'System and method for generating a reset signal for synchronization of a signal'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/734438 | System and method for generating a reset signal for synchronization of a signal | Apr 11, 2007 | Issued |
Array
(
[id] => 58621
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[patent_issue_date] => 2010-08-03
[patent_title] => 'Method and apparatus for resolving clock management issues in emulation involving both interpreted and translated code'
[patent_app_type] => utility
[patent_app_number] => 11/696699
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/696699 | Method and apparatus for resolving clock management issues in emulation involving both interpreted and translated code | Apr 3, 2007 | Issued |
Array
(
[id] => 4722506
[patent_doc_number] => 20080244302
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'SYSTEM AND METHOD TO ENABLE AN EVENT TIMER IN A MULTIPLE EVENT TIMER OPERATING ENVIRONMENT'
[patent_app_type] => utility
[patent_app_number] => 11/693873
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/693873 | System and method to enable an event timer in a multiple event timer operating environment | Mar 29, 2007 | Issued |
Array
(
[id] => 4722458
[patent_doc_number] => 20080244281
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[patent_title] => 'Method and System for Associating Power Consumption with a Network Address'
[patent_app_type] => utility
[patent_app_number] => 11/693886
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[firstpage_image] =>[orig_patent_app_number] => 11693886
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/693886 | Method and system for associating power consumption of a server with a network address assigned to the server | Mar 29, 2007 | Issued |
Array
(
[id] => 4590041
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[patent_title] => 'Hybrid operating systems for battery powered computing systems'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/693659 | Hybrid operating systems for battery powered computing systems | Mar 28, 2007 | Issued |
Array
(
[id] => 48868
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[patent_title] => 'High resolution timer circuit and time count method for suppressing increase in storage capacity'
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Array
(
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[patent_title] => 'INFORMATION-PROCESSING APPARATUS CAPABLE OF MANAGING PLURALITY OF EXECUTION SPACES'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/687746 | Management of time information within a plurality of execution spaces | Mar 18, 2007 | Issued |
Array
(
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[patent_title] => 'APPARATUS FOR REMOTE FLASHING OF A BIOS MEMORY IN A DATA PROCESSING SYSTEM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/686966 | APPARATUS FOR REMOTE FLASHING OF A BIOS MEMORY IN A DATA PROCESSING SYSTEM | Mar 15, 2007 | Abandoned |
Array
(
[id] => 96951
[patent_doc_number] => 07734940
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[patent_issue_date] => 2010-06-08
[patent_title] => 'Data communication device has data signal generation circuit and transmission circuit on basis of reference voltage and received signal'
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[patent_app_number] => 11/687233
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[pdf_file] => patents/07/734/07734940.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/687233 | Data communication device has data signal generation circuit and transmission circuit on basis of reference voltage and received signal | Mar 15, 2007 | Issued |