Search

Fernando N. Hidalgo

Examiner (ID: 543, Phone: (571)270-3306 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1664
Issued Applications
1514
Pending Applications
94
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9525742 [patent_doc_number] => 08750025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Data cells with drivers and methods of making and operating the same' [patent_app_type] => utility [patent_app_number] => 13/965488 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 63 [patent_no_of_words] => 10828 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965488 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/965488
Data cells with drivers and methods of making and operating the same Aug 12, 2013 Issued
Array ( [id] => 9866593 [patent_doc_number] => 20150046612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'MEMORY DEVICE FORMED WITH A SEMICONDUCTOR INTERPOSER' [patent_app_type] => utility [patent_app_number] => 13/963768 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3497 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963768 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/963768
Memory device formed with a semiconductor interposer Aug 8, 2013 Issued
Array ( [id] => 10041786 [patent_doc_number] => 09082498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'N-well switching circuit' [patent_app_type] => utility [patent_app_number] => 13/962702 [patent_app_country] => US [patent_app_date] => 2013-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13962702 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/962702
N-well switching circuit Aug 7, 2013 Issued
Array ( [id] => 10073447 [patent_doc_number] => 09111811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Analog memory cell circuit for the LTPS TFT-LCD' [patent_app_type] => utility [patent_app_number] => 13/962537 [patent_app_country] => US [patent_app_date] => 2013-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6203 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 963 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13962537 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/962537
Analog memory cell circuit for the LTPS TFT-LCD Aug 7, 2013 Issued
Array ( [id] => 10028567 [patent_doc_number] => 09070472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling' [patent_app_type] => utility [patent_app_number] => 13/952885 [patent_app_country] => US [patent_app_date] => 2013-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 17816 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13952885 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/952885
Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling Jul 28, 2013 Issued
Array ( [id] => 9415223 [patent_doc_number] => 08699269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-15 [patent_title] => 'Systems and methods for improving error distributions in multi-level cell memory systems' [patent_app_type] => utility [patent_app_number] => 13/951766 [patent_app_country] => US [patent_app_date] => 2013-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6017 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13951766 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/951766
Systems and methods for improving error distributions in multi-level cell memory systems Jul 25, 2013 Issued
Array ( [id] => 9884307 [patent_doc_number] => 08971084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Context protection for a column interleaved memory' [patent_app_type] => utility [patent_app_number] => 13/948914 [patent_app_country] => US [patent_app_date] => 2013-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3093 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13948914 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/948914
Context protection for a column interleaved memory Jul 22, 2013 Issued
Array ( [id] => 9148856 [patent_doc_number] => 20130303379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'HYBRID SUPERCONDUCTING-MAGNETIC MEMORY CELL AND ARRAY' [patent_app_type] => utility [patent_app_number] => 13/943356 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943356 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943356
Hybrid superconducting-magnetic memory cell and array Jul 15, 2013 Issued
Array ( [id] => 10899833 [patent_doc_number] => 08923062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-30 [patent_title] => 'Generating read thresholds using gradient descent and without side information' [patent_app_type] => utility [patent_app_number] => 13/935714 [patent_app_country] => US [patent_app_date] => 2013-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6649 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935714 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935714
Generating read thresholds using gradient descent and without side information Jul 4, 2013 Issued
Array ( [id] => 9764076 [patent_doc_number] => 08848412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-30 [patent_title] => 'Ternary content addressable memory' [patent_app_type] => utility [patent_app_number] => 13/935710 [patent_app_country] => US [patent_app_date] => 2013-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5975 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935710 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935710
Ternary content addressable memory Jul 4, 2013 Issued
Array ( [id] => 9329287 [patent_doc_number] => 20140056069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'NONVOLATILE MEMORY DEVICE HAVING NEAR/FAR MEMORY CELL GROUPINGS AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 13/935596 [patent_app_country] => US [patent_app_date] => 2013-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16154 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935596 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935596
NONVOLATILE MEMORY DEVICE HAVING NEAR/FAR MEMORY CELL GROUPINGS AND DATA PROCESSING METHOD Jul 4, 2013 Abandoned
Array ( [id] => 10079654 [patent_doc_number] => 09117504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Volume select for affecting a state of a non-selected memory volume' [patent_app_type] => utility [patent_app_number] => 13/935318 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 11674 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935318 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935318
Volume select for affecting a state of a non-selected memory volume Jul 2, 2013 Issued
Array ( [id] => 9791218 [patent_doc_number] => 20150003162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'Detecting Programmed Word Lines Based On NAND String Current' [patent_app_type] => utility [patent_app_number] => 13/932384 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932384 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/932384
Detecting programmed word lines based on NAND string current Jun 30, 2013 Issued
Array ( [id] => 9733302 [patent_doc_number] => 20140269011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'MULTI-PHASE GROUND-REFERENCED SINGLE-ENDED SIGNALING' [patent_app_type] => utility [patent_app_number] => 13/933058 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15641 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933058 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933058
Multi-phase ground-referenced single-ended signaling Jun 30, 2013 Issued
Array ( [id] => 11252782 [patent_doc_number] => 09478294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Dummy memory erase or program method protected against detection' [patent_app_type] => utility [patent_app_number] => 14/406334 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5201 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14406334 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/406334
Dummy memory erase or program method protected against detection Jun 27, 2013 Issued
Array ( [id] => 9203956 [patent_doc_number] => 20140003133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'SRAM LAYOUTS' [patent_app_type] => utility [patent_app_number] => 13/929076 [patent_app_country] => US [patent_app_date] => 2013-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9322 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13929076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/929076
SRAM layouts Jun 26, 2013 Issued
Array ( [id] => 11796519 [patent_doc_number] => 09406362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Memory tile access and selection patterns' [patent_app_type] => utility [patent_app_number] => 13/919758 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8533 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919758 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/919758
Memory tile access and selection patterns Jun 16, 2013 Issued
Array ( [id] => 9664064 [patent_doc_number] => 08811062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Variable resistance memory device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/919120 [patent_app_country] => US [patent_app_date] => 2013-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 6662 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13919120 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/919120
Variable resistance memory device and method of manufacturing the same Jun 16, 2013 Issued
Array ( [id] => 11200871 [patent_doc_number] => 09431089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Optimizing power in a memory device' [patent_app_type] => utility [patent_app_number] => 14/405910 [patent_app_country] => US [patent_app_date] => 2013-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14405910 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/405910
Optimizing power in a memory device Jun 9, 2013 Issued
Array ( [id] => 9190184 [patent_doc_number] => 20130329499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'MEMORY CELL STRING BASED ON GATED-DIODE CELL AND MEMORY ARRAY USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/912578 [patent_app_country] => US [patent_app_date] => 2013-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13912578 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/912578
Memory cell string based on gated-diode cell and memory array using the same Jun 6, 2013 Issued
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