Search

Fernando N. Hidalgo

Examiner (ID: 515, Phone: (571)270-3306 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
1669
Issued Applications
1517
Pending Applications
96
Abandoned Applications
91

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19252504 [patent_doc_number] => 20240203501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => PROGRAMMING OPERATION USING CACHE REGISTER RELEASE IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/404282 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404282
Programming operation using cache register release in a memory sub-system Jan 3, 2024 Issued
Array ( [id] => 19566698 [patent_doc_number] => 12141470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Feedback for multi-level signaling in a memory device [patent_app_type] => utility [patent_app_number] => 18/403512 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 23290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403512
Feedback for multi-level signaling in a memory device Jan 2, 2024 Issued
Array ( [id] => 19321206 [patent_doc_number] => 20240242752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => TECHNIQUES FOR DATA REFRESH BASED ON ENVIRONMENTAL CONDITIONS [patent_app_type] => utility [patent_app_number] => 18/403468 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403468 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403468
Techniques for data refresh based on environmental conditions Jan 2, 2024 Issued
Array ( [id] => 20530161 [patent_doc_number] => 12548602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Memory device and manufacturing method of the memory device [patent_app_type] => utility [patent_app_number] => 18/401945 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 3509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18401945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/401945
Memory device and manufacturing method of the memory device Jan 1, 2024 Issued
Array ( [id] => 19123376 [patent_doc_number] => 11967370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-23 [patent_title] => Lifetime mixed level non-volatile memory system [patent_app_type] => utility [patent_app_number] => 18/390193 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3823 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390193 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/390193
Lifetime mixed level non-volatile memory system Dec 19, 2023 Issued
Array ( [id] => 20274670 [patent_doc_number] => 12444454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Memory devices selecting and protecting a possible attacked word line based on the previous refreshed word lines and the relevant methods [patent_app_type] => utility [patent_app_number] => 18/538079 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4749 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538079
Memory devices selecting and protecting a possible attacked word line based on the previous refreshed word lines and the relevant methods Dec 12, 2023 Issued
Array ( [id] => 19269040 [patent_doc_number] => 20240212744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY DEVICE TO PRECHARGE BITLINES PRIOR TO SENSING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/537685 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537685
MEMORY DEVICE TO PRECHARGE BITLINES PRIOR TO SENSING MEMORY CELLS Dec 11, 2023 Pending
Array ( [id] => 19087890 [patent_doc_number] => 20240114691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => ANALOG NON-VOLATILE MEMORY DEVICE USING POLY FERRORELECTRIC FILM WITH RANDOM POLARIZATION DIRECTIONS [patent_app_type] => utility [patent_app_number] => 18/525301 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525301
Analog non-volatile memory device using poly ferrorelectric film with random polarization directions Nov 29, 2023 Issued
Array ( [id] => 19221194 [patent_doc_number] => 20240185898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => SYNDROME DECODING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/523366 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18523366 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/523366
Syndrome decoding system Nov 28, 2023 Issued
Array ( [id] => 19830022 [patent_doc_number] => 12250829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Memory device, and integrated circuit device [patent_app_type] => utility [patent_app_number] => 18/521109 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 13109 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521109 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521109
Memory device, and integrated circuit device Nov 27, 2023 Issued
Array ( [id] => 19054419 [patent_doc_number] => 20240096388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY CELL AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/518736 [patent_app_country] => US [patent_app_date] => 2023-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518736 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518736
Memory cell and method of operating the same Nov 23, 2023 Issued
Array ( [id] => 19237071 [patent_doc_number] => 20240194266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/518496 [patent_app_country] => US [patent_app_date] => 2023-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518496
Semiconductor device and data storage system including semiconductor device Nov 22, 2023 Issued
Array ( [id] => 20080566 [patent_doc_number] => 12354641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Memory devices selecting and protecting a possible attacked word line based on the previous refreshed word lines and the relevant methods [patent_app_type] => utility [patent_app_number] => 18/514043 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18514043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/514043
Memory devices selecting and protecting a possible attacked word line based on the previous refreshed word lines and the relevant methods Nov 19, 2023 Issued
Array ( [id] => 20243919 [patent_doc_number] => 12424249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Buffer chip, and semiconductor package including the buffer chip and a memory chip [patent_app_type] => utility [patent_app_number] => 18/509039 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8746 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509039 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/509039
Buffer chip, and semiconductor package including the buffer chip and a memory chip Nov 13, 2023 Issued
Array ( [id] => 19384350 [patent_doc_number] => 20240274220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => ACCESS LINE CONTACTS FOR AN ACCESS LINE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/505532 [patent_app_country] => US [patent_app_date] => 2023-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18505532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/505532
Access line contacts for an access line in a memory device Nov 8, 2023 Issued
Array ( [id] => 19646218 [patent_doc_number] => 20240420738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MEMORY DEVICE HAVING SUPPORT STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/504905 [patent_app_country] => US [patent_app_date] => 2023-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504905 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/504905
Memory device having support structure Nov 7, 2023 Issued
Array ( [id] => 19123375 [patent_doc_number] => 11967369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Lifetime mixed level non-volatile memory system [patent_app_type] => utility [patent_app_number] => 18/387546 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3775 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 536 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18387546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/387546
Lifetime mixed level non-volatile memory system Nov 6, 2023 Issued
Array ( [id] => 19005723 [patent_doc_number] => 20240069794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => Memory Circuit Including an Array Control Inhibitor [patent_app_type] => utility [patent_app_number] => 18/503315 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503315 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/503315
Memory circuit including an array control inhibitor Nov 6, 2023 Issued
Array ( [id] => 20404260 [patent_doc_number] => 12494240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Memory module related to signal integrity of clock [patent_app_type] => utility [patent_app_number] => 18/500937 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18500937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/500937
Memory module related to signal integrity of clock Nov 1, 2023 Issued
Array ( [id] => 19626860 [patent_doc_number] => 12165707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Memory with FRAM and SRAM of IC [patent_app_type] => utility [patent_app_number] => 18/492964 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492964
Memory with FRAM and SRAM of IC Oct 23, 2023 Issued
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