
Fernando N. Hidalgo
Examiner (ID: 7872, Phone: (571)270-3306 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 1637 |
| Issued Applications | 1494 |
| Pending Applications | 89 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19926937
[patent_doc_number] => 12301236
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Equalizer for removing inter symbol interference of data signal by increasing pulse widths of logic low level and logic high level of data signal
[patent_app_type] => utility
[patent_app_number] => 18/331223
[patent_app_country] => US
[patent_app_date] => 2023-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 8463
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331223
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/331223 | Equalizer for removing inter symbol interference of data signal by increasing pulse widths of logic low level and logic high level of data signal | Jun 7, 2023 | Issued |
Array
(
[id] => 18677976
[patent_doc_number] => 20230315623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => SELF-SEEDED RANDOMIZER FOR DATA RANDOMIZATION IN FLASH MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/206958
[patent_app_country] => US
[patent_app_date] => 2023-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19225
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206958
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/206958 | Self-seeded randomizer for data randomization in flash memory | Jun 6, 2023 | Issued |
Array
(
[id] => 19964663
[patent_doc_number] => 12334178
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-17
[patent_title] => Integrated circuit, system and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 18/330049
[patent_app_country] => US
[patent_app_date] => 2023-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 32
[patent_no_of_words] => 26589
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330049
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/330049 | Integrated circuit, system and method of forming the same | Jun 5, 2023 | Issued |
Array
(
[id] => 18661035
[patent_doc_number] => 20230307048
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => METHODS AND SYSTEMS FOR AN ANALOG CAM WITH FUZZY SEARCH
[patent_app_type] => utility
[patent_app_number] => 18/326813
[patent_app_country] => US
[patent_app_date] => 2023-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6887
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326813
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/326813 | Methods and systems for an analog cam with fuzzy search | May 30, 2023 | Issued |
Array
(
[id] => 18652805
[patent_doc_number] => 20230298645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => MEMORY DEVICE, OPERATING METHOD OF THE MEMORY DEVICE AND MEMORY SYSTEM COMPRISING THE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/323550
[patent_app_country] => US
[patent_app_date] => 2023-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7574
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323550
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/323550 | Memory device, operating method of the memory device and memory system comprising the memory device | May 24, 2023 | Issued |
Array
(
[id] => 20443031
[patent_doc_number] => 12513877
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Integrated circuit including static random access memory device
[patent_app_type] => utility
[patent_app_number] => 18/201465
[patent_app_country] => US
[patent_app_date] => 2023-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3371
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201465
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/201465 | Integrated circuit including static random access memory device | May 23, 2023 | Issued |
Array
(
[id] => 18851170
[patent_doc_number] => 20230413574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => NON-VOLATILE MEMORY INCLUDING NEGATIVE CAPACITANCE BLOCKING OXIDE LAYER, OPERATING METHOD OF THE SAME AND MANUFACTURING METHOD OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/197189
[patent_app_country] => US
[patent_app_date] => 2023-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7991
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197189
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/197189 | Non-volatile memory including negative capacitance blocking oxide layer, operating method of the same and manufacturing method of the same | May 14, 2023 | Issued |
Array
(
[id] => 19828599
[patent_doc_number] => 12249390
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-11
[patent_title] => Memory systems with vertical integration
[patent_app_type] => utility
[patent_app_number] => 18/316743
[patent_app_country] => US
[patent_app_date] => 2023-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 28
[patent_no_of_words] => 9287
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316743
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/316743 | Memory systems with vertical integration | May 11, 2023 | Issued |
Array
(
[id] => 18682410
[patent_doc_number] => 20230320087
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/314527
[patent_app_country] => US
[patent_app_date] => 2023-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27272
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314527
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/314527 | Memory system | May 8, 2023 | Issued |
Array
(
[id] => 18977232
[patent_doc_number] => 20240057324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-15
[patent_title] => SEMICONDUCTOR MEMORY DEVICE CAPABLE OF EXPANDING BANK CAPACITY ADAPTIVELY TO PACKAGE SIZE AND METHOD OF DESIGNING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/143756
[patent_app_country] => US
[patent_app_date] => 2023-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11097
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143756
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/143756 | Semiconductor memory device capable of expanding bank capacity adaptively to package size and method of designing the same | May 4, 2023 | Issued |
Array
(
[id] => 18810620
[patent_doc_number] => 20230384955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => MEMORY CONTROLLER SEARCHING FOR DATA INPUT/OUTPUT VOLTAGE, MEMORY SYSTEM, AND OPERATING METHOD OF THE MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/310959
[patent_app_country] => US
[patent_app_date] => 2023-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8184
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310959
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/310959 | Memory controller searching for data input/output voltage, memory system, and operating method of the memory system | May 1, 2023 | Issued |
Array
(
[id] => 18585727
[patent_doc_number] => 20230267991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => SRAM Design with Four-Poly-Pitch
[patent_app_type] => utility
[patent_app_number] => 18/306757
[patent_app_country] => US
[patent_app_date] => 2023-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14274
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306757
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/306757 | SRAM design with four-poly-pitch | Apr 24, 2023 | Issued |
Array
(
[id] => 20636567
[patent_doc_number] => 12597448
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 18/138196
[patent_app_country] => US
[patent_app_date] => 2023-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 83
[patent_no_of_words] => 28907
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138196
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/138196 | Semiconductor device | Apr 23, 2023 | Issued |
Array
(
[id] => 18787866
[patent_doc_number] => 20230376235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => MEMORY DEVICE INTERFACE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 18/138527
[patent_app_country] => US
[patent_app_date] => 2023-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12485
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138527
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/138527 | Memory device interface and method | Apr 23, 2023 | Issued |
Array
(
[id] => 18741606
[patent_doc_number] => 20230350587
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-02
[patent_title] => PEAK POWER MANAGEMENT PRIORITY OVERRIDE
[patent_app_type] => utility
[patent_app_number] => 18/137002
[patent_app_country] => US
[patent_app_date] => 2023-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14026
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137002
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/137002 | Peak power management priority override | Apr 19, 2023 | Issued |
Array
(
[id] => 18555006
[patent_doc_number] => 20230253022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-10
[patent_title] => Memory Array Test Structure and Method of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 18/302560
[patent_app_country] => US
[patent_app_date] => 2023-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14224
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18302560
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/302560 | Memory array test structure and method of forming the same | Apr 17, 2023 | Issued |
Array
(
[id] => 19500122
[patent_doc_number] => 20240339140
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => MEMORY DEVICE, READ CLOCK GENERATION CIRCUIT, AND METHOD FOR CONTROLLING READ OPERATION IN MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/297094
[patent_app_country] => US
[patent_app_date] => 2023-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7136
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18297094
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/297094 | Memory device, read clock generation circuit, and method for controlling read operation in memory device | Apr 6, 2023 | Issued |
Array
(
[id] => 20647219
[patent_doc_number] => 12602162
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-14
[patent_title] => Memory training enhancements
[patent_app_type] => utility
[patent_app_number] => 18/129300
[patent_app_country] => US
[patent_app_date] => 2023-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18129300
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/129300 | MEMORY TRAINING ENHANCEMENTS | Mar 30, 2023 | Issued |
Array
(
[id] => 19812813
[patent_doc_number] => 12244228
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Voltage regulator device, corresponding method and data storage system
[patent_app_type] => utility
[patent_app_number] => 18/187831
[patent_app_country] => US
[patent_app_date] => 2023-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 8178
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18187831
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/187831 | Voltage regulator device, corresponding method and data storage system | Mar 21, 2023 | Issued |
Array
(
[id] => 20552941
[patent_doc_number] => 12563750
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-24
[patent_title] => Semiconductor memory device and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 18/181148
[patent_app_country] => US
[patent_app_date] => 2023-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 5527
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181148
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/181148 | Semiconductor memory device and method of manufacturing the same | Mar 8, 2023 | Issued |