
Fernando N. Hidalgo
Examiner (ID: 515, Phone: (571)270-3306 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 1669 |
| Issued Applications | 1517 |
| Pending Applications | 96 |
| Abandoned Applications | 91 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20266810
[patent_doc_number] => 12437806
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-07
[patent_title] => Semiconductor device and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 18/344058
[patent_app_country] => US
[patent_app_date] => 2023-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 2809
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344058
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/344058 | Semiconductor device and operating method thereof | Jun 28, 2023 | Issued |
Array
(
[id] => 18730131
[patent_doc_number] => 20230344429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => SEMICONDUCTOR DEVICE RELATED TO CALIBRATING TERMINATION RESISTANCE
[patent_app_type] => utility
[patent_app_number] => 18/343537
[patent_app_country] => US
[patent_app_date] => 2023-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15182
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343537
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/343537 | Semiconductor device related to calibrating termination resistance | Jun 27, 2023 | Issued |
Array
(
[id] => 18728019
[patent_doc_number] => 20230342312
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-26
[patent_title] => STORAGE DEVICE AND COMPUTER DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/342252
[patent_app_country] => US
[patent_app_date] => 2023-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9993
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342252
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/342252 | STORAGE DEVICE AND COMPUTER DEVICE | Jun 26, 2023 | Abandoned |
Array
(
[id] => 19305231
[patent_doc_number] => 20240233811
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2024-07-11
[patent_title] => BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/340216
[patent_app_country] => US
[patent_app_date] => 2023-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8699
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340216
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/340216 | Bit line sense amplifier of semiconductor memory device and semiconductor memory device having the same | Jun 22, 2023 | Issued |
Array
(
[id] => 19305231
[patent_doc_number] => 20240233811
[patent_country] => US
[patent_kind] => A9
[patent_issue_date] => 2024-07-11
[patent_title] => BIT LINE SENSE AMPLIFIER OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/340216
[patent_app_country] => US
[patent_app_date] => 2023-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8699
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340216
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/340216 | Bit line sense amplifier of semiconductor memory device and semiconductor memory device having the same | Jun 22, 2023 | Issued |
Array
(
[id] => 19515426
[patent_doc_number] => 20240347112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => MEMORY PERFORMING RESET OPERATION AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/339069
[patent_app_country] => US
[patent_app_date] => 2023-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3355
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18339069
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/339069 | Memory performing reset operation and operating method thereof | Jun 20, 2023 | Issued |
Array
(
[id] => 20245928
[patent_doc_number] => 12426273
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-23
[patent_title] => Magnetoresistance memory device and method for manufacturing magnetoresistance memory device
[patent_app_type] => utility
[patent_app_number] => 18/337576
[patent_app_country] => US
[patent_app_date] => 2023-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 2247
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337576
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/337576 | Magnetoresistance memory device and method for manufacturing magnetoresistance memory device | Jun 19, 2023 | Issued |
Array
(
[id] => 20868013
[patent_doc_number] => 12694921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-07-28
[patent_title] => Dynamic memory operations
[patent_app_type] => utility
[patent_app_number] => 18/333135
[patent_app_country] => US
[patent_app_date] => 2023-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6059
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333135
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/333135 | Dynamic Memory Operations | Jun 11, 2023 | Issued |
Array
(
[id] => 19617256
[patent_doc_number] => 20240402936
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-05
[patent_title] => CLOCK CONTROL CIRCUIT, MEMORY STORAGE DEVICE AND CLOCK CONTROL METHOD
[patent_app_type] => utility
[patent_app_number] => 18/332766
[patent_app_country] => US
[patent_app_date] => 2023-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5378
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -30
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332766
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/332766 | Clock control circuit, memory storage device and clock control method | Jun 11, 2023 | Issued |
Array
(
[id] => 19483737
[patent_doc_number] => 20240331779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/331937
[patent_app_country] => US
[patent_app_date] => 2023-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5150
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331937
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/331937 | Semiconductor device and operating method of semiconductor device | Jun 8, 2023 | Issued |
Array
(
[id] => 19085920
[patent_doc_number] => 20240112721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-04
[patent_title] => DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
[patent_app_type] => utility
[patent_app_number] => 18/208050
[patent_app_country] => US
[patent_app_date] => 2023-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9579
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18208050
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/208050 | Double data rate (DDR) memory controller apparatus and method | Jun 8, 2023 | Issued |
Array
(
[id] => 19926937
[patent_doc_number] => 12301236
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Equalizer for removing inter symbol interference of data signal by increasing pulse widths of logic low level and logic high level of data signal
[patent_app_type] => utility
[patent_app_number] => 18/331223
[patent_app_country] => US
[patent_app_date] => 2023-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 17
[patent_no_of_words] => 8463
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331223
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/331223 | Equalizer for removing inter symbol interference of data signal by increasing pulse widths of logic low level and logic high level of data signal | Jun 7, 2023 | Issued |
Array
(
[id] => 18677976
[patent_doc_number] => 20230315623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => SELF-SEEDED RANDOMIZER FOR DATA RANDOMIZATION IN FLASH MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/206958
[patent_app_country] => US
[patent_app_date] => 2023-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19225
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206958
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/206958 | Self-seeded randomizer for data randomization in flash memory | Jun 6, 2023 | Issued |
Array
(
[id] => 19964663
[patent_doc_number] => 12334178
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-17
[patent_title] => Integrated circuit, system and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 18/330049
[patent_app_country] => US
[patent_app_date] => 2023-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 32
[patent_no_of_words] => 26589
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330049
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/330049 | Integrated circuit, system and method of forming the same | Jun 5, 2023 | Issued |
Array
(
[id] => 18661035
[patent_doc_number] => 20230307048
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => METHODS AND SYSTEMS FOR AN ANALOG CAM WITH FUZZY SEARCH
[patent_app_type] => utility
[patent_app_number] => 18/326813
[patent_app_country] => US
[patent_app_date] => 2023-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6887
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326813
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/326813 | Methods and systems for an analog cam with fuzzy search | May 30, 2023 | Issued |
Array
(
[id] => 18652805
[patent_doc_number] => 20230298645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => MEMORY DEVICE, OPERATING METHOD OF THE MEMORY DEVICE AND MEMORY SYSTEM COMPRISING THE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/323550
[patent_app_country] => US
[patent_app_date] => 2023-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7574
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323550
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/323550 | Memory device, operating method of the memory device and memory system comprising the memory device | May 24, 2023 | Issued |
Array
(
[id] => 20443031
[patent_doc_number] => 12513877
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Integrated circuit including static random access memory device
[patent_app_type] => utility
[patent_app_number] => 18/201465
[patent_app_country] => US
[patent_app_date] => 2023-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3371
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201465
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/201465 | Integrated circuit including static random access memory device | May 23, 2023 | Issued |
Array
(
[id] => 18851170
[patent_doc_number] => 20230413574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => NON-VOLATILE MEMORY INCLUDING NEGATIVE CAPACITANCE BLOCKING OXIDE LAYER, OPERATING METHOD OF THE SAME AND MANUFACTURING METHOD OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/197189
[patent_app_country] => US
[patent_app_date] => 2023-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7991
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197189
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/197189 | Non-volatile memory including negative capacitance blocking oxide layer, operating method of the same and manufacturing method of the same | May 14, 2023 | Issued |
Array
(
[id] => 19828599
[patent_doc_number] => 12249390
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-11
[patent_title] => Memory systems with vertical integration
[patent_app_type] => utility
[patent_app_number] => 18/316743
[patent_app_country] => US
[patent_app_date] => 2023-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 28
[patent_no_of_words] => 9287
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316743
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/316743 | Memory systems with vertical integration | May 11, 2023 | Issued |
Array
(
[id] => 18682410
[patent_doc_number] => 20230320087
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/314527
[patent_app_country] => US
[patent_app_date] => 2023-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27272
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314527
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/314527 | Memory system | May 8, 2023 | Issued |