
Ferris Lander
Examiner (ID: 7708)
| Most Active Art Unit | 1103 |
| Art Unit(s) | 1108, 1303, 1802, 3307, 1103, 1209, 2899, 1754, 1306 |
| Total Applications | 1021 |
| Issued Applications | 801 |
| Pending Applications | 19 |
| Abandoned Applications | 201 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4930847
[patent_doc_number] => 20080001622
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'Semiconductor memory device with on die termination circuit'
[patent_app_type] => utility
[patent_app_number] => 11/647176
[patent_app_country] => US
[patent_app_date] => 2006-12-29
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[firstpage_image] =>[orig_patent_app_number] => 11647176
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/647176 | Semiconductor memory device with on die termination circuit | Dec 28, 2006 | Issued |
Array
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[patent_doc_number] => 07812632
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-12
[patent_title] => 'Apparatus for on-die termination of semiconductor memory and method of operating the same'
[patent_app_type] => utility
[patent_app_number] => 11/646467
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/646467 | Apparatus for on-die termination of semiconductor memory and method of operating the same | Dec 27, 2006 | Issued |
Array
(
[id] => 243825
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[patent_issue_date] => 2009-09-15
[patent_title] => 'I/O cell capable of finely controlling drive strength'
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[patent_app_date] => 2006-12-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/646461 | I/O cell capable of finely controlling drive strength | Dec 27, 2006 | Issued |
Array
(
[id] => 271031
[patent_doc_number] => 07564268
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[patent_issue_date] => 2009-07-21
[patent_title] => 'Low power logic output buffer'
[patent_app_type] => utility
[patent_app_number] => 11/557320
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[firstpage_image] =>[orig_patent_app_number] => 11557320
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/557320 | Low power logic output buffer | Nov 6, 2006 | Issued |
Array
(
[id] => 5214378
[patent_doc_number] => 20070103458
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[patent_issue_date] => 2007-05-10
[patent_title] => 'DRIVING IC AND DISPLAY DEVICE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/556873 | DRIVING IC AND DISPLAY DEVICE | Nov 5, 2006 | Abandoned |
Array
(
[id] => 7590810
[patent_doc_number] => 07663401
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[patent_issue_date] => 2010-02-16
[patent_title] => 'Multiplexer initialization systems and methods'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/556528 | Multiplexer initialization systems and methods | Nov 2, 2006 | Issued |
Array
(
[id] => 5214125
[patent_doc_number] => 20070103205
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[patent_issue_date] => 2007-05-10
[patent_title] => 'SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS'
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[patent_app_number] => 11/555349
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[pdf_file] => publications/A1/0103/20070103205.pdf
[firstpage_image] =>[orig_patent_app_number] => 11555349
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/555349 | LVDS input circuit with connection to input of output driver | Oct 31, 2006 | Issued |
Array
(
[id] => 4891246
[patent_doc_number] => 20080100343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-01
[patent_title] => 'Source Driver and Level Shifting Apparatus Thereof'
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[firstpage_image] =>[orig_patent_app_number] => 11555492
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/555492 | Source Driver and Level Shifting Apparatus Thereof | Oct 31, 2006 | Abandoned |
Array
(
[id] => 861732
[patent_doc_number] => 07372305
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-05-13
[patent_title] => 'Scannable dynamic logic latch circuit'
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[firstpage_image] =>[orig_patent_app_number] => 11554685
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/554685 | Scannable dynamic logic latch circuit | Oct 30, 2006 | Issued |
Array
(
[id] => 4667629
[patent_doc_number] => 20080042689
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-02-21
[patent_title] => 'VOLTAGE BUFFER AND SOURCE DRIVER THEREOF'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/554044 | Voltage buffer and source driver thereof | Oct 29, 2006 | Issued |
Array
(
[id] => 4986411
[patent_doc_number] => 20070152749
[patent_country] => US
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[patent_title] => 'Transmission Circuit and Related Method'
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[firstpage_image] =>[orig_patent_app_number] => 11538060
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/538060 | Transmission circuit and related method | Oct 2, 2006 | Issued |
Array
(
[id] => 5163545
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/309802 | SIGNAL TRANSMITTING CIRCUIT | Sep 27, 2006 | Abandoned |
Array
(
[id] => 65462
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/527882 | Method of and system for verifying configuration data | Sep 26, 2006 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/528117 | Circuits and methods of concatenating FIFOs | Sep 26, 2006 | Issued |
Array
(
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Array
(
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Array
(
[id] => 869903
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Array
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Array
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Array
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