Search

Ferris Lander

Examiner (ID: 7708)

Most Active Art Unit
1103
Art Unit(s)
1108, 1303, 1802, 3307, 1103, 1209, 2899, 1754, 1306
Total Applications
1021
Issued Applications
801
Pending Applications
19
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4930847 [patent_doc_number] => 20080001622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Semiconductor memory device with on die termination circuit' [patent_app_type] => utility [patent_app_number] => 11/647176 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3197 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20080001622.pdf [firstpage_image] =>[orig_patent_app_number] => 11647176 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/647176
Semiconductor memory device with on die termination circuit Dec 28, 2006 Issued
Array ( [id] => 5887 [patent_doc_number] => 07812632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Apparatus for on-die termination of semiconductor memory and method of operating the same' [patent_app_type] => utility [patent_app_number] => 11/646467 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/812/07812632.pdf [firstpage_image] =>[orig_patent_app_number] => 11646467 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646467
Apparatus for on-die termination of semiconductor memory and method of operating the same Dec 27, 2006 Issued
Array ( [id] => 243825 [patent_doc_number] => 07589562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'I/O cell capable of finely controlling drive strength' [patent_app_type] => utility [patent_app_number] => 11/646461 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3002 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589562.pdf [firstpage_image] =>[orig_patent_app_number] => 11646461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646461
I/O cell capable of finely controlling drive strength Dec 27, 2006 Issued
Array ( [id] => 271031 [patent_doc_number] => 07564268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Low power logic output buffer' [patent_app_type] => utility [patent_app_number] => 11/557320 [patent_app_country] => US [patent_app_date] => 2006-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2924 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/564/07564268.pdf [firstpage_image] =>[orig_patent_app_number] => 11557320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/557320
Low power logic output buffer Nov 6, 2006 Issued
Array ( [id] => 5214378 [patent_doc_number] => 20070103458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'DRIVING IC AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/556873 [patent_app_country] => US [patent_app_date] => 2006-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5341 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103458.pdf [firstpage_image] =>[orig_patent_app_number] => 11556873 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556873
DRIVING IC AND DISPLAY DEVICE Nov 5, 2006 Abandoned
Array ( [id] => 7590810 [patent_doc_number] => 07663401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-16 [patent_title] => 'Multiplexer initialization systems and methods' [patent_app_type] => utility [patent_app_number] => 11/556528 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4177 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/663/07663401.pdf [firstpage_image] =>[orig_patent_app_number] => 11556528 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556528
Multiplexer initialization systems and methods Nov 2, 2006 Issued
Array ( [id] => 5214125 [patent_doc_number] => 20070103205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'SIMULTANEOUS LVDS I/O SIGNALING METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/555349 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11021 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103205.pdf [firstpage_image] =>[orig_patent_app_number] => 11555349 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555349
LVDS input circuit with connection to input of output driver Oct 31, 2006 Issued
Array ( [id] => 4891246 [patent_doc_number] => 20080100343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Source Driver and Level Shifting Apparatus Thereof' [patent_app_type] => utility [patent_app_number] => 11/555492 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2667 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20080100343.pdf [firstpage_image] =>[orig_patent_app_number] => 11555492 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555492
Source Driver and Level Shifting Apparatus Thereof Oct 31, 2006 Abandoned
Array ( [id] => 861732 [patent_doc_number] => 07372305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-13 [patent_title] => 'Scannable dynamic logic latch circuit' [patent_app_type] => utility [patent_app_number] => 11/554685 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372305.pdf [firstpage_image] =>[orig_patent_app_number] => 11554685 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/554685
Scannable dynamic logic latch circuit Oct 30, 2006 Issued
Array ( [id] => 4667629 [patent_doc_number] => 20080042689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'VOLTAGE BUFFER AND SOURCE DRIVER THEREOF' [patent_app_type] => utility [patent_app_number] => 11/554044 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11140 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20080042689.pdf [firstpage_image] =>[orig_patent_app_number] => 11554044 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/554044
Voltage buffer and source driver thereof Oct 29, 2006 Issued
Array ( [id] => 4986411 [patent_doc_number] => 20070152749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Transmission Circuit and Related Method' [patent_app_type] => utility [patent_app_number] => 11/538060 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9086 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20070152749.pdf [firstpage_image] =>[orig_patent_app_number] => 11538060 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538060
Transmission circuit and related method Oct 2, 2006 Issued
Array ( [id] => 5163545 [patent_doc_number] => 20070285129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'SIGNAL TRANSMITTING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/309802 [patent_app_country] => US [patent_app_date] => 2006-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 932 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20070285129.pdf [firstpage_image] =>[orig_patent_app_number] => 11309802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/309802
SIGNAL TRANSMITTING CIRCUIT Sep 27, 2006 Abandoned
Array ( [id] => 65462 [patent_doc_number] => 07759968 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Method of and system for verifying configuration data' [patent_app_type] => utility [patent_app_number] => 11/527882 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7438 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759968.pdf [firstpage_image] =>[orig_patent_app_number] => 11527882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527882
Method of and system for verifying configuration data Sep 26, 2006 Issued
Array ( [id] => 304642 [patent_doc_number] => 07535789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-19 [patent_title] => 'Circuits and methods of concatenating FIFOs' [patent_app_type] => utility [patent_app_number] => 11/528117 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5691 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535789.pdf [firstpage_image] =>[orig_patent_app_number] => 11528117 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/528117
Circuits and methods of concatenating FIFOs Sep 26, 2006 Issued
Array ( [id] => 134275 [patent_doc_number] => 07696779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'System LSI' [patent_app_type] => utility [patent_app_number] => 11/526816 [patent_app_country] => US [patent_app_date] => 2006-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3280 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696779.pdf [firstpage_image] =>[orig_patent_app_number] => 11526816 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/526816
System LSI Sep 25, 2006 Issued
Array ( [id] => 364024 [patent_doc_number] => 07482840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/525999 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8986 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482840.pdf [firstpage_image] =>[orig_patent_app_number] => 11525999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/525999
Semiconductor integrated circuit Sep 24, 2006 Issued
Array ( [id] => 869903 [patent_doc_number] => 07365564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Apparatus and method for controlling on die termination' [patent_app_type] => utility [patent_app_number] => 11/525951 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4104 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/365/07365564.pdf [firstpage_image] =>[orig_patent_app_number] => 11525951 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/525951
Apparatus and method for controlling on die termination Sep 24, 2006 Issued
Array ( [id] => 4936835 [patent_doc_number] => 20080074149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Buffer with inductance-based capacitive-load reduction' [patent_app_type] => utility [patent_app_number] => 11/526306 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2340 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074149.pdf [firstpage_image] =>[orig_patent_app_number] => 11526306 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/526306
Buffer with inductance-based capacitive-load reduction Sep 24, 2006 Issued
Array ( [id] => 4936827 [patent_doc_number] => 20080074141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Adjustable interface buffer circuit between a programmable logic device and a dedicated device' [patent_app_type] => utility [patent_app_number] => 11/525275 [patent_app_country] => US [patent_app_date] => 2006-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3454 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074141.pdf [firstpage_image] =>[orig_patent_app_number] => 11525275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/525275
Adjustable interface buffer circuit between a programmable logic device and a dedicated device Sep 20, 2006 Issued
Array ( [id] => 4702315 [patent_doc_number] => 20080061837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Low Supply Voltage, Large Output Swing, Source-Terminated Output Driver for High Speed AC-coupled Double-Termination Serial Links' [patent_app_type] => utility [patent_app_number] => 11/467528 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5228 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061837.pdf [firstpage_image] =>[orig_patent_app_number] => 11467528 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/467528
Low Supply Voltage, Large Output Swing, Source-Terminated Output Driver for High Speed AC-coupled Double-Termination Serial Links Aug 24, 2006 Abandoned
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