Ferris Lander

Array ( [id] => 4560301 [patent_doc_number] => 07821296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Stacked buffers' [patent_app_type] => utility [patent_app_number] => 11/498994 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3102 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/821/07821296.pdf [firstpage_image] =>[orig_patent_app_number] => 11498994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 160469 [patent_doc_number] => 07675313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-09 [patent_title] => 'Methods and systems for storing a security key using programmable fuses' [patent_app_type] => utility [patent_app_number] => 11/498645 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5091 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/675/07675313.pdf [firstpage_image] =>[orig_patent_app_number] => 11498645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 225420 [patent_doc_number] => 07605606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-20 [patent_title] => 'Area efficient routing architectures for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/498646 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/605/07605606.pdf [firstpage_image] =>[orig_patent_app_number] => 11498646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4655299 [patent_doc_number] => 20080024160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'On-Chip Resistor Calibration For Line Termination' [patent_app_type] => utility [patent_app_number] => 11/459880 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5989 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20080024160.pdf [firstpage_image] =>[orig_patent_app_number] => 11459880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4597544 [patent_doc_number] => 07982499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Capacitive node isolation for electrostatic discharge circuit' [patent_app_type] => utility [patent_app_number] => 11/459734 [patent_app_country] => US [patent_app_date] => 2006-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2140 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/982/07982499.pdf [firstpage_image] =>[orig_patent_app_number] => 11459734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 873763 [patent_doc_number] => 07362137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'High speed voltage level shifter circuits' [patent_app_type] => utility [patent_app_number] => 11/459381 [patent_app_country] => US [patent_app_date] => 2006-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3409 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362137.pdf [firstpage_image] =>[orig_patent_app_number] => 11459381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4645115 [patent_doc_number] => 08022723 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-20 [patent_title] => 'Dynamic termination-impedance control for bidirectional I/O pins' [patent_app_type] => utility [patent_app_number] => 11/458675 [patent_app_country] => US [patent_app_date] => 2006-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 8269 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/022/08022723.pdf [firstpage_image] =>[orig_patent_app_number] => 11458675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4907591 [patent_doc_number] => 20080018357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'AUTOMATIC TERMINATION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/458320 [patent_app_country] => US [patent_app_date] => 2006-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20080018357.pdf [firstpage_image] =>[orig_patent_app_number] => 11458320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5240197 [patent_doc_number] => 20070018688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Digital Logic Unit' [patent_app_type] => utility [patent_app_number] => 11/457929 [patent_app_country] => US [patent_app_date] => 2006-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2692 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018688.pdf [firstpage_image] =>[orig_patent_app_number] => 11457929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5014615 [patent_doc_number] => 20070257823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-08 [patent_title] => 'Chip-To-Chip Digital Transmission Circuit Delivering Power Over Signal Lines' [patent_app_type] => utility [patent_app_number] => 11/381135 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20070257823.pdf [firstpage_image] =>[orig_patent_app_number] => 11381135 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5123976 [patent_doc_number] => 20070236247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Techniques For Providing Flexible On-Chip Termination Control on Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 11/381356 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20070236247.pdf [firstpage_image] =>[orig_patent_app_number] => 11381356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4497103 [patent_doc_number] => 07956641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-07 [patent_title] => 'Low voltage interface circuit' [patent_app_type] => utility [patent_app_number] => 11/380333 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5291 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/956/07956641.pdf [firstpage_image] =>[orig_patent_app_number] => 11380333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5917325 [patent_doc_number] => 20060238037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Differential current driving type transmission system' [patent_app_type] => utility [patent_app_number] => 11/411571 [patent_app_country] => US [patent_app_date] => 2006-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5322 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20060238037.pdf [firstpage_image] =>[orig_patent_app_number] => 11411571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5208610 [patent_doc_number] => 20070247194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Output buffer to drive AC-coupled terminated transmission lines' [patent_app_type] => utility [patent_app_number] => 11/410680 [patent_app_country] => US [patent_app_date] => 2006-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3888 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247194.pdf [firstpage_image] =>[orig_patent_app_number] => 11410680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 873777 [patent_doc_number] => 07362141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Logic device with low EMI' [patent_app_type] => utility [patent_app_number] => 11/407941 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2011 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362141.pdf [firstpage_image] =>[orig_patent_app_number] => 11407941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5918478 [patent_doc_number] => 20060238527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'HIGH SPEED LOGIC SIGNAL LEVEL SHIFTER' [patent_app_type] => utility [patent_app_number] => 11/379509 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4876 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20060238527.pdf [firstpage_image] =>[orig_patent_app_number] => 11379509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4477974 [patent_doc_number] => 07868660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Serial communications bus with active pullup' [patent_app_type] => utility [patent_app_number] => 11/379473 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4160 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/868/07868660.pdf [firstpage_image] =>[orig_patent_app_number] => 11379473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4731743 [patent_doc_number] => 20080048721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'INPUT BUFFER IN ULTRADEEP SUBMICRON PROCESS' [patent_app_type] => utility [patent_app_number] => 11/379381 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1543 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048721.pdf [firstpage_image] =>[orig_patent_app_number] => 11379381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4584529 [patent_doc_number] => 07834658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-16 [patent_title] => 'Interface generation for coupling to a high-bandwidth interface' [patent_app_type] => utility [patent_app_number] => 11/405895 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11525 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/834/07834658.pdf [firstpage_image] =>[orig_patent_app_number] => 11405895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 243820 [patent_doc_number] => 07589557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-15 [patent_title] => 'Reversible input/output delay line for bidirectional input/output blocks' [patent_app_type] => utility [patent_app_number] => 11/405901 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589557.pdf [firstpage_image] =>[orig_patent_app_number] => 11405901 [rel_patent_id] =>[rel_patent_doc_number] =>)