Search

Ferris Lander

Examiner (ID: 7708)

Most Active Art Unit
1103
Art Unit(s)
1108, 1303, 1802, 3307, 1103, 1209, 2899, 1754, 1306
Total Applications
1021
Issued Applications
801
Pending Applications
19
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5175575 [patent_doc_number] => 20070176633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Output circuit' [patent_app_type] => utility [patent_app_number] => 11/405524 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5706 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20070176633.pdf [firstpage_image] =>[orig_patent_app_number] => 11405524 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/405524
Output circuit Apr 17, 2006 Abandoned
Array ( [id] => 5127047 [patent_doc_number] => 20070239318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Receiver particularly for a meter-bus' [patent_app_type] => utility [patent_app_number] => 11/399051 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2679 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20070239318.pdf [firstpage_image] =>[orig_patent_app_number] => 11399051 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/399051
Receiver particularly for a meter-bus Apr 4, 2006 Issued
Array ( [id] => 134293 [patent_doc_number] => 07696786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Precision differential level shifter' [patent_app_type] => utility [patent_app_number] => 11/369316 [patent_app_country] => US [patent_app_date] => 2006-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5951 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696786.pdf [firstpage_image] =>[orig_patent_app_number] => 11369316 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/369316
Precision differential level shifter Mar 5, 2006 Issued
Array ( [id] => 5617411 [patent_doc_number] => 20060186943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Ultra-low-power voltage transform circuit' [patent_app_type] => utility [patent_app_number] => 11/358029 [patent_app_country] => US [patent_app_date] => 2006-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2583 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20060186943.pdf [firstpage_image] =>[orig_patent_app_number] => 11358029 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/358029
Ultra-low-power voltage transform circuit Feb 21, 2006 Abandoned
Array ( [id] => 5111059 [patent_doc_number] => 20070194974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-23 [patent_title] => 'Structure and method for reducing the current consumption of a capacitive load' [patent_app_type] => utility [patent_app_number] => 11/357068 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3242 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20070194974.pdf [firstpage_image] =>[orig_patent_app_number] => 11357068 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357068
Structure and method for reducing the current consumption of a capacitive load Feb 20, 2006 Abandoned
Array ( [id] => 841074 [patent_doc_number] => 07391229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-24 [patent_title] => 'Techniques for serially transmitting on-chip termination control signals' [patent_app_type] => utility [patent_app_number] => 11/356867 [patent_app_country] => US [patent_app_date] => 2006-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5157 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391229.pdf [firstpage_image] =>[orig_patent_app_number] => 11356867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356867
Techniques for serially transmitting on-chip termination control signals Feb 17, 2006 Issued
Array ( [id] => 861776 [patent_doc_number] => 07372331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Receiver circuit' [patent_app_type] => utility [patent_app_number] => 11/357905 [patent_app_country] => US [patent_app_date] => 2006-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4178 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372331.pdf [firstpage_image] =>[orig_patent_app_number] => 11357905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/357905
Receiver circuit Feb 16, 2006 Issued
Array ( [id] => 7597135 [patent_doc_number] => 07619443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-17 [patent_title] => 'Programmable logic device architectures and methods for implementing logic in those architectures' [patent_app_type] => utility [patent_app_number] => 11/356762 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4784 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/619/07619443.pdf [firstpage_image] =>[orig_patent_app_number] => 11356762 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/356762
Programmable logic device architectures and methods for implementing logic in those architectures Feb 15, 2006 Issued
Array ( [id] => 5020041 [patent_doc_number] => 20070146007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Level shift delay equalization circuit and methodology' [patent_app_type] => utility [patent_app_number] => 11/315146 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3754 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20070146007.pdf [firstpage_image] =>[orig_patent_app_number] => 11315146 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/315146
Level shift delay equalization circuit and methodology Dec 22, 2005 Issued
Array ( [id] => 5653324 [patent_doc_number] => 20060139059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Level shift circuit and method' [patent_app_type] => utility [patent_app_number] => 11/313860 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7837 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20060139059.pdf [firstpage_image] =>[orig_patent_app_number] => 11313860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313860
Level shift circuit and method Dec 19, 2005 Abandoned
Array ( [id] => 5117365 [patent_doc_number] => 20070139079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Reducing power noise in differential drivers' [patent_app_type] => utility [patent_app_number] => 11/314855 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1139 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20070139079.pdf [firstpage_image] =>[orig_patent_app_number] => 11314855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314855
Reducing power noise in differential drivers Dec 19, 2005 Abandoned
Array ( [id] => 5117357 [patent_doc_number] => 20070139071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Configurable on-die termination' [patent_app_type] => utility [patent_app_number] => 11/313054 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3059 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20070139071.pdf [firstpage_image] =>[orig_patent_app_number] => 11313054 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313054
Configurable on-die termination Dec 18, 2005 Issued
Array ( [id] => 5117356 [patent_doc_number] => 20070139070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Buffer having predriver to help improve symmetry of rise and fall transitions in an output signal' [patent_app_type] => utility [patent_app_number] => 11/313076 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6178 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20070139070.pdf [firstpage_image] =>[orig_patent_app_number] => 11313076 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313076
Buffer having predriver to help improve symmetry of rise and fall transitions in an output signal Dec 18, 2005 Abandoned
Array ( [id] => 5531200 [patent_doc_number] => 20090230988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'ELECTRONIC DEVICE HAVING LOGIC CIRCUITRY AND METHOD FOR DESIGNING LOGIC CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 11/720213 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4754 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20090230988.pdf [firstpage_image] =>[orig_patent_app_number] => 11720213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/720213
ELECTRONIC DEVICE HAVING LOGIC CIRCUITRY AND METHOD FOR DESIGNING LOGIC CIRCUITRY Nov 27, 2005 Abandoned
Array ( [id] => 5741619 [patent_doc_number] => 20060087342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Interconnect structure and method in programmable devices' [patent_app_type] => utility [patent_app_number] => 11/261420 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3084 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087342.pdf [firstpage_image] =>[orig_patent_app_number] => 11261420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261420
Interconnect structure and method in programmable devices Oct 26, 2005 Issued
Array ( [id] => 5032231 [patent_doc_number] => 20070096770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Cascaded pass-gate test circuit with interposed split-output drive devices' [patent_app_type] => utility [patent_app_number] => 11/260571 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096770.pdf [firstpage_image] =>[orig_patent_app_number] => 11260571 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260571
Cascaded pass-gate test circuit with interposed split-output drive devices Oct 26, 2005 Issued
Array ( [id] => 5478092 [patent_doc_number] => 20090201049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'INTEGRATED CIRCUIT WITH INPUT AND/OR OUTPUT BOLTON PADS WITH INTEGRATED LOGIC' [patent_app_type] => utility [patent_app_number] => 11/576142 [patent_app_country] => US [patent_app_date] => 2005-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7825 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20090201049.pdf [firstpage_image] =>[orig_patent_app_number] => 11576142 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/576142
Integrated circuit with input and/or output bolton pads with integrated logic Sep 4, 2005 Issued
Array ( [id] => 817611 [patent_doc_number] => 07411419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-12 [patent_title] => 'Input/output systems and methods' [patent_app_type] => utility [patent_app_number] => 11/200941 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2865 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/411/07411419.pdf [firstpage_image] =>[orig_patent_app_number] => 11200941 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200941
Input/output systems and methods Aug 8, 2005 Issued
Array ( [id] => 5796856 [patent_doc_number] => 20060033533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/199931 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5575 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20060033533.pdf [firstpage_image] =>[orig_patent_app_number] => 11199931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199931
Semiconductor device Aug 7, 2005 Abandoned
Array ( [id] => 63885 [patent_doc_number] => 07764081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-27 [patent_title] => 'Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunity' [patent_app_type] => utility [patent_app_number] => 11/197936 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3394 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/764/07764081.pdf [firstpage_image] =>[orig_patent_app_number] => 11197936 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197936
Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunity Aug 4, 2005 Issued
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