
Ferris Lander
Examiner (ID: 7708)
| Most Active Art Unit | 1103 |
| Art Unit(s) | 1108, 1303, 1802, 3307, 1103, 1209, 2899, 1754, 1306 |
| Total Applications | 1021 |
| Issued Applications | 801 |
| Pending Applications | 19 |
| Abandoned Applications | 201 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 153223
[patent_doc_number] => 07679397
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-03-16
[patent_title] => 'Techniques for precision biasing output driver for a calibrated on-chip termination circuit'
[patent_app_type] => utility
[patent_app_number] => 11/198049
[patent_app_country] => US
[patent_app_date] => 2005-08-05
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[pdf_file] => patents/07/679/07679397.pdf
[firstpage_image] =>[orig_patent_app_number] => 11198049
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/198049 | Techniques for precision biasing output driver for a calibrated on-chip termination circuit | Aug 4, 2005 | Issued |
Array
(
[id] => 311597
[patent_doc_number] => 07528629
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'Low-power low-voltage multi-level variable-resistor line driver'
[patent_app_type] => utility
[patent_app_number] => 11/198070
[patent_app_country] => US
[patent_app_date] => 2005-08-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/528/07528629.pdf
[firstpage_image] =>[orig_patent_app_number] => 11198070
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/198070 | Low-power low-voltage multi-level variable-resistor line driver | Aug 3, 2005 | Issued |
Array
(
[id] => 5049486
[patent_doc_number] => 20070030030
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-08
[patent_title] => 'Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals'
[patent_app_type] => utility
[patent_app_number] => 11/195897
[patent_app_country] => US
[patent_app_date] => 2005-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => publications/A1/0030/20070030030.pdf
[firstpage_image] =>[orig_patent_app_number] => 11195897
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/195897 | Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals | Aug 2, 2005 | Issued |
Array
(
[id] => 44012
[patent_doc_number] => 07782090
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-24
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/193337
[patent_app_country] => US
[patent_app_date] => 2005-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
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[pdf_file] => patents/07/782/07782090.pdf
[firstpage_image] =>[orig_patent_app_number] => 11193337
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/193337 | Semiconductor device | Jul 31, 2005 | Issued |
Array
(
[id] => 817615
[patent_doc_number] => 07411423
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-12
[patent_title] => 'Logic activation circuit'
[patent_app_type] => utility
[patent_app_number] => 11/194495
[patent_app_country] => US
[patent_app_date] => 2005-08-01
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/411/07411423.pdf
[firstpage_image] =>[orig_patent_app_number] => 11194495
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/194495 | Logic activation circuit | Jul 31, 2005 | Issued |
Array
(
[id] => 5202843
[patent_doc_number] => 20070024322
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'Leakage current reduction scheme for domino circuits'
[patent_app_type] => utility
[patent_app_number] => 11/194946
[patent_app_country] => US
[patent_app_date] => 2005-08-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0024/20070024322.pdf
[firstpage_image] =>[orig_patent_app_number] => 11194946
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/194946 | Leakage current reduction scheme for domino circuits | Jul 31, 2005 | Abandoned |
Array
(
[id] => 4554636
[patent_doc_number] => 07961000
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-06-14
[patent_title] => 'Impedance matching circuit and method'
[patent_app_type] => utility
[patent_app_number] => 11/193791
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[patent_app_date] => 2005-07-29
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/961/07961000.pdf
[firstpage_image] =>[orig_patent_app_number] => 11193791
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/193791 | Impedance matching circuit and method | Jul 28, 2005 | Issued |
Array
(
[id] => 5202838
[patent_doc_number] => 20070024317
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-01
[patent_title] => 'Apparatus for obtaining precision integrated resistors'
[patent_app_type] => utility
[patent_app_number] => 11/193833
[patent_app_country] => US
[patent_app_date] => 2005-07-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0024/20070024317.pdf
[firstpage_image] =>[orig_patent_app_number] => 11193833
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/193833 | Apparatus for obtaining precision integrated resistors | Jul 28, 2005 | Abandoned |
Array
(
[id] => 5768728
[patent_doc_number] => 20050265526
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => 'Data transmission apparatus and a data receiving apparatus used for the same'
[patent_app_type] => utility
[patent_app_number] => 11/138476
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[patent_app_date] => 2005-05-27
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[pdf_file] => publications/A1/0265/20050265526.pdf
[firstpage_image] =>[orig_patent_app_number] => 11138476
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/138476 | Data transmission apparatus and a data receiving apparatus used for the same | May 26, 2005 | Issued |
Array
(
[id] => 4580185
[patent_doc_number] => 07825684
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-02
[patent_title] => 'Variable width management for a memory of a configurable IC'
[patent_app_type] => utility
[patent_app_number] => 11/081850
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[patent_app_date] => 2005-03-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/825/07825684.pdf
[firstpage_image] =>[orig_patent_app_number] => 11081850
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/081850 | Variable width management for a memory of a configurable IC | Mar 14, 2005 | Issued |
Array
(
[id] => 188519
[patent_doc_number] => 07650545
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[patent_issue_date] => 2010-01-19
[patent_title] => 'Programmable interconnect for reconfigurable system-on-chip'
[patent_app_type] => utility
[patent_app_number] => 10/379043
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[patent_app_date] => 2003-03-04
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[pdf_file] => patents/07/650/07650545.pdf
[firstpage_image] =>[orig_patent_app_number] => 10379043
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/379043 | Programmable interconnect for reconfigurable system-on-chip | Mar 3, 2003 | Issued |