Search

Fetsum Abraham

Examiner (ID: 7354)

Most Active Art Unit
2826
Art Unit(s)
2811, 2825, 2515, 2826, 2818, 2508
Total Applications
1055
Issued Applications
981
Pending Applications
32
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7607216 [patent_doc_number] => 07098500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge' [patent_app_type] => utility [patent_app_number] => 11/178215 [patent_app_country] => US [patent_app_date] => 2005-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 2581 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/098/07098500.pdf [firstpage_image] =>[orig_patent_app_number] => 11178215 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/178215
Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge Jul 7, 2005 Issued
Array ( [id] => 7072742 [patent_doc_number] => 20050146008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/057495 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 92 [patent_figures_cnt] => 92 [patent_no_of_words] => 23607 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146008.pdf [firstpage_image] =>[orig_patent_app_number] => 11057495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057495
Semiconductor device Feb 14, 2005 Issued
Array ( [id] => 717064 [patent_doc_number] => 07053423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-30 [patent_title] => 'Thyristor having a first emitter with relatively lightly doped portion to the base' [patent_app_type] => utility [patent_app_number] => 10/982443 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4438 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/053/07053423.pdf [firstpage_image] =>[orig_patent_app_number] => 10982443 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982443
Thyristor having a first emitter with relatively lightly doped portion to the base Nov 4, 2004 Issued
Array ( [id] => 7198136 [patent_doc_number] => 20050051779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/969875 [patent_app_country] => US [patent_app_date] => 2004-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5306 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20050051779.pdf [firstpage_image] =>[orig_patent_app_number] => 10969875 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/969875
Semiconductor device Oct 21, 2004 Issued
Array ( [id] => 7080503 [patent_doc_number] => 20050045883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Thin film semiconductor device and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 10/961094 [patent_app_country] => US [patent_app_date] => 2004-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6403 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20050045883.pdf [firstpage_image] =>[orig_patent_app_number] => 10961094 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/961094
Thin film semiconductor device and method for manufacturing same Oct 11, 2004 Issued
Array ( [id] => 7241869 [patent_doc_number] => 20050073011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Semiconductor device having a HMP metal gate' [patent_app_type] => utility [patent_app_number] => 10/959213 [patent_app_country] => US [patent_app_date] => 2004-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5374 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073011.pdf [firstpage_image] =>[orig_patent_app_number] => 10959213 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/959213
Semiconductor device having a HMP metal gate Oct 5, 2004 Issued
Array ( [id] => 6903400 [patent_doc_number] => 20050098795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'High voltage device with ESD protection' [patent_app_type] => utility [patent_app_number] => 10/956063 [patent_app_country] => US [patent_app_date] => 2004-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2026 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20050098795.pdf [firstpage_image] =>[orig_patent_app_number] => 10956063 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956063
High voltage device with ESD protection Oct 3, 2004 Issued
Array ( [id] => 7147525 [patent_doc_number] => 20050023529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Strained semiconductor by wafer bonding with misorientation' [patent_app_type] => utility [patent_app_number] => 10/931749 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6604 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20050023529.pdf [firstpage_image] =>[orig_patent_app_number] => 10931749 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931749
Strained semiconductor by wafer bonding with misorientation Aug 30, 2004 Issued
Array ( [id] => 7273034 [patent_doc_number] => 20040232485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/870921 [patent_app_country] => US [patent_app_date] => 2004-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10199 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232485.pdf [firstpage_image] =>[orig_patent_app_number] => 10870921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/870921
Semiconductor device Jun 20, 2004 Issued
Array ( [id] => 7404950 [patent_doc_number] => 20040262715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Semiconductor device and manufacturing method for the same' [patent_app_type] => new [patent_app_number] => 10/866673 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6703 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20040262715.pdf [firstpage_image] =>[orig_patent_app_number] => 10866673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/866673
Semiconductor device and manufacturing method for the same Jun 14, 2004 Issued
Array ( [id] => 7053874 [patent_doc_number] => 20050275046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'MULTI-LAYER GATE STACK STRUCTURE COMPRISING A METAL LAYER FOR A FET DEVICE, AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 10/865763 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4553 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20050275046.pdf [firstpage_image] =>[orig_patent_app_number] => 10865763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/865763
Multi-layer gate stack structure comprising a metal layer for a FET device, and method for fabricating the same Jun 13, 2004 Issued
Array ( [id] => 675729 [patent_doc_number] => 07087473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Method of forming conventional complementary MOS transistors and complementary heterojunction MOS transistors on common substrate' [patent_app_type] => utility [patent_app_number] => 10/866093 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 47 [patent_no_of_words] => 9354 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087473.pdf [firstpage_image] =>[orig_patent_app_number] => 10866093 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/866093
Method of forming conventional complementary MOS transistors and complementary heterojunction MOS transistors on common substrate Jun 13, 2004 Issued
Array ( [id] => 692031 [patent_doc_number] => 07075155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-11 [patent_title] => 'Structure for protecting a semiconductor circuit from electrostatic discharge and a method for forming the structure' [patent_app_type] => utility [patent_app_number] => 10/866114 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 3752 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/075/07075155.pdf [firstpage_image] =>[orig_patent_app_number] => 10866114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/866114
Structure for protecting a semiconductor circuit from electrostatic discharge and a method for forming the structure Jun 13, 2004 Issued
Array ( [id] => 774805 [patent_doc_number] => 07002217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Electrostatic discharge mitigation structure and methods thereof using a dissipative capacitor with voltage dependent resistive material' [patent_app_type] => utility [patent_app_number] => 10/866544 [patent_app_country] => US [patent_app_date] => 2004-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2466 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002217.pdf [firstpage_image] =>[orig_patent_app_number] => 10866544 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/866544
Electrostatic discharge mitigation structure and methods thereof using a dissipative capacitor with voltage dependent resistive material Jun 11, 2004 Issued
Array ( [id] => 664048 [patent_doc_number] => 07102159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Ultra thin image sensor package structure and method for fabrication' [patent_app_type] => utility [patent_app_number] => 10/865983 [patent_app_country] => US [patent_app_date] => 2004-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5404 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102159.pdf [firstpage_image] =>[orig_patent_app_number] => 10865983 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/865983
Ultra thin image sensor package structure and method for fabrication Jun 11, 2004 Issued
Array ( [id] => 788357 [patent_doc_number] => 06987290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Current-jump-control circuit including abrupt metal-insulator phase transition device' [patent_app_type] => utility [patent_app_number] => 10/866274 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2249 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/987/06987290.pdf [firstpage_image] =>[orig_patent_app_number] => 10866274 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/866274
Current-jump-control circuit including abrupt metal-insulator phase transition device Jun 9, 2004 Issued
Array ( [id] => 956209 [patent_doc_number] => 06955959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Method of making a memory structure having a multilayered contact and a storage capacitor with a composite dielectric layer of crystalized niobium pentoxide and tantalum pentoxide films' [patent_app_type] => utility [patent_app_number] => 10/853133 [patent_app_country] => US [patent_app_date] => 2004-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 21678 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/955/06955959.pdf [firstpage_image] =>[orig_patent_app_number] => 10853133 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/853133
Method of making a memory structure having a multilayered contact and a storage capacitor with a composite dielectric layer of crystalized niobium pentoxide and tantalum pentoxide films May 25, 2004 Issued
Array ( [id] => 7205964 [patent_doc_number] => 20050258446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'LED assembly with vented circuit board' [patent_app_type] => utility [patent_app_number] => 10/847343 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5097 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20050258446.pdf [firstpage_image] =>[orig_patent_app_number] => 10847343 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/847343
LED assembly with vented circuit board May 17, 2004 Issued
Array ( [id] => 7407201 [patent_doc_number] => 20040227191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Evaluation method of a field effect transistor' [patent_app_type] => new [patent_app_number] => 10/845133 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4187 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20040227191.pdf [firstpage_image] =>[orig_patent_app_number] => 10845133 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/845133
Evaluation method of a field effect transistor May 13, 2004 Issued
Array ( [id] => 785717 [patent_doc_number] => 06989557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Bipolar junction transistor and fabricating method' [patent_app_type] => utility [patent_app_number] => 10/709569 [patent_app_country] => US [patent_app_date] => 2004-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3840 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989557.pdf [firstpage_image] =>[orig_patent_app_number] => 10709569 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709569
Bipolar junction transistor and fabricating method May 13, 2004 Issued
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