Search

Fetsum Abraham

Examiner (ID: 13571)

Most Active Art Unit
2826
Art Unit(s)
2825, 2515, 2508, 2826, 2811, 2818
Total Applications
1055
Issued Applications
981
Pending Applications
32
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
09/365596 MOLD LOCKING GROUND RING Jul 29, 1999 Abandoned
Array ( [id] => 1448090 [patent_doc_number] => 06369434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Nitrogen co-implantation to form shallow junction-extensions of p-type metal oxide semiconductor field effect transistors' [patent_app_type] => B1 [patent_app_number] => 09/363742 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3426 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369434.pdf [firstpage_image] =>[orig_patent_app_number] => 09363742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363742
Nitrogen co-implantation to form shallow junction-extensions of p-type metal oxide semiconductor field effect transistors Jul 29, 1999 Issued
Array ( [id] => 1476430 [patent_doc_number] => 06388334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'System and method for circuit rebuilding via backside access' [patent_app_type] => B1 [patent_app_number] => 09/361464 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388334.pdf [firstpage_image] =>[orig_patent_app_number] => 09361464 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361464
System and method for circuit rebuilding via backside access Jul 26, 1999 Issued
Array ( [id] => 4410482 [patent_doc_number] => 06271545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Asymmetrical thyristor with blocking/sweep voltage independent of temperature behavior' [patent_app_type] => 1 [patent_app_number] => 9/355061 [patent_app_country] => US [patent_app_date] => 1999-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1841 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271545.pdf [firstpage_image] =>[orig_patent_app_number] => 355061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/355061
Asymmetrical thyristor with blocking/sweep voltage independent of temperature behavior Jul 21, 1999 Issued
Array ( [id] => 7631022 [patent_doc_number] => 06635910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Silicon strain gage having a thin layer of highly conductive silicon' [patent_app_type] => B1 [patent_app_number] => 09/359012 [patent_app_country] => US [patent_app_date] => 1999-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2128 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635910.pdf [firstpage_image] =>[orig_patent_app_number] => 09359012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359012
Silicon strain gage having a thin layer of highly conductive silicon Jul 21, 1999 Issued
Array ( [id] => 4388560 [patent_doc_number] => 06278192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Semiconductor device with encapsulating material composed of silica' [patent_app_type] => 1 [patent_app_number] => 9/354734 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6308 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278192.pdf [firstpage_image] =>[orig_patent_app_number] => 354734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354734
Semiconductor device with encapsulating material composed of silica Jul 15, 1999 Issued
Array ( [id] => 4317895 [patent_doc_number] => 06316810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Display switch with double layered gate insulation and resinous interlayer dielectric' [patent_app_type] => 1 [patent_app_number] => 9/350176 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 11699 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316810.pdf [firstpage_image] =>[orig_patent_app_number] => 350176 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/350176
Display switch with double layered gate insulation and resinous interlayer dielectric Jul 8, 1999 Issued
Array ( [id] => 4360233 [patent_doc_number] => 06218679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Display panel and display device using the same' [patent_app_type] => 1 [patent_app_number] => 9/347863 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 83 [patent_no_of_words] => 41550 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218679.pdf [firstpage_image] =>[orig_patent_app_number] => 347863 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347863
Display panel and display device using the same Jul 8, 1999 Issued
Array ( [id] => 4112982 [patent_doc_number] => 06057557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Semiconductor substrate semiconductor device and liquid crystal display device' [patent_app_type] => 1 [patent_app_number] => 9/349076 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 12574 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057557.pdf [firstpage_image] =>[orig_patent_app_number] => 349076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/349076
Semiconductor substrate semiconductor device and liquid crystal display device Jul 7, 1999 Issued
Array ( [id] => 1568327 [patent_doc_number] => 06376859 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Variable porosity porous silicon isolation' [patent_app_type] => B1 [patent_app_number] => 09/346763 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 2192 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376859.pdf [firstpage_image] =>[orig_patent_app_number] => 09346763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346763
Variable porosity porous silicon isolation Jun 30, 1999 Issued
Array ( [id] => 4424681 [patent_doc_number] => 06225665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Semiconductor device having multiple source regions' [patent_app_type] => 1 [patent_app_number] => 9/346266 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 8029 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225665.pdf [firstpage_image] =>[orig_patent_app_number] => 346266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346266
Semiconductor device having multiple source regions Jun 30, 1999 Issued
Array ( [id] => 1522326 [patent_doc_number] => 06414391 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Module assembly for stacked BGA packages with a common bus bar in the assembly' [patent_app_type] => B1 [patent_app_number] => 09/343746 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3928 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414391.pdf [firstpage_image] =>[orig_patent_app_number] => 09343746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343746
Module assembly for stacked BGA packages with a common bus bar in the assembly Jun 29, 1999 Issued
Array ( [id] => 4365893 [patent_doc_number] => 06255676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Charge coupled device with nonreflective coating' [patent_app_type] => 1 [patent_app_number] => 9/343642 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2243 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255676.pdf [firstpage_image] =>[orig_patent_app_number] => 343642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343642
Charge coupled device with nonreflective coating Jun 29, 1999 Issued
Array ( [id] => 4294268 [patent_doc_number] => 06211563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Semiconductor package with an improved leadframe' [patent_app_type] => 1 [patent_app_number] => 9/343516 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1563 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211563.pdf [firstpage_image] =>[orig_patent_app_number] => 343516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343516
Semiconductor package with an improved leadframe Jun 29, 1999 Issued
Array ( [id] => 4414016 [patent_doc_number] => 06310402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Semiconductor die having input/output cells and contact pads in the periphery of a substrate' [patent_app_type] => 1 [patent_app_number] => 9/344494 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310402.pdf [firstpage_image] =>[orig_patent_app_number] => 344494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344494
Semiconductor die having input/output cells and contact pads in the periphery of a substrate Jun 24, 1999 Issued
Array ( [id] => 4324973 [patent_doc_number] => 06249044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Opaque metallization to cover flip chip die surface for light sensitive semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/335440 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2821 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249044.pdf [firstpage_image] =>[orig_patent_app_number] => 335440 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335440
Opaque metallization to cover flip chip die surface for light sensitive semiconductor devices Jun 16, 1999 Issued
Array ( [id] => 4282720 [patent_doc_number] => 06281567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Substrate for mounting semiconductor chip with parallel conductive lines' [patent_app_type] => 1 [patent_app_number] => 9/333515 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3586 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281567.pdf [firstpage_image] =>[orig_patent_app_number] => 333515 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333515
Substrate for mounting semiconductor chip with parallel conductive lines Jun 14, 1999 Issued
Array ( [id] => 4373432 [patent_doc_number] => 06274922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Fabrication of high power semiconductor device with a heat sink and integration with planar microstrip circuitry' [patent_app_type] => 1 [patent_app_number] => 9/334165 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3902 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274922.pdf [firstpage_image] =>[orig_patent_app_number] => 334165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334165
Fabrication of high power semiconductor device with a heat sink and integration with planar microstrip circuitry Jun 14, 1999 Issued
Array ( [id] => 4414156 [patent_doc_number] => 06265753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Interconnect dielectric compositions, preparation thereof, and integrated circuit devices fabricated therewith' [patent_app_type] => 1 [patent_app_number] => 9/330285 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 7094 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265753.pdf [firstpage_image] =>[orig_patent_app_number] => 330285 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330285
Interconnect dielectric compositions, preparation thereof, and integrated circuit devices fabricated therewith Jun 10, 1999 Issued
Array ( [id] => 4414496 [patent_doc_number] => 06229206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Bonding pad test configuration' [patent_app_type] => 1 [patent_app_number] => 9/326366 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1633 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229206.pdf [firstpage_image] =>[orig_patent_app_number] => 326366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/326366
Bonding pad test configuration Jun 3, 1999 Issued
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