
Fetsum Abraham
Examiner (ID: 1991)
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2818, 2508, 2826, 2811, 2825, 2515 |
| Total Applications | 1055 |
| Issued Applications | 981 |
| Pending Applications | 32 |
| Abandoned Applications | 42 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4151974
[patent_doc_number] => 06064092
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Semiconductor-on-insulator substrates containing electrically insulating mesas'
[patent_app_type] => 1
[patent_app_number] => 9/291416
[patent_app_country] => US
[patent_app_date] => 1999-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 2005
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[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/064/06064092.pdf
[firstpage_image] =>[orig_patent_app_number] => 291416
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/291416 | Semiconductor-on-insulator substrates containing electrically insulating mesas | Apr 12, 1999 | Issued |
Array
(
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[patent_doc_number] => 06642557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-11-04
[patent_title] => 'Isolated junction structure for a MOSFET'
[patent_app_type] => B2
[patent_app_number] => 09/289424
[patent_app_country] => US
[patent_app_date] => 1999-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/642/06642557.pdf
[firstpage_image] =>[orig_patent_app_number] => 09289424
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/289424 | Isolated junction structure for a MOSFET | Apr 8, 1999 | Issued |
Array
(
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[patent_issue_date] => 2001-04-24
[patent_title] => 'Semiconductor device having partially and fully depleted SOI elements on a common substrate'
[patent_app_type] => 1
[patent_app_number] => 9/288314
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[patent_app_date] => 1999-04-08
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[patent_drawing_sheets_cnt] => 5
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[patent_words_short_claim] => 116
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[pdf_file] => patents/06/222/06222234.pdf
[firstpage_image] =>[orig_patent_app_number] => 288314
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/288314 | Semiconductor device having partially and fully depleted SOI elements on a common substrate | Apr 7, 1999 | Issued |
Array
(
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[patent_doc_number] => 06297529
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Semiconductor device with multilayered gate structure'
[patent_app_type] => 1
[patent_app_number] => 9/286334
[patent_app_country] => US
[patent_app_date] => 1999-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/06/297/06297529.pdf
[firstpage_image] =>[orig_patent_app_number] => 286334
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/286334 | Semiconductor device with multilayered gate structure | Apr 4, 1999 | Issued |
Array
(
[id] => 4319641
[patent_doc_number] => 06242779
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Selective silicide thin-film transistor having polysilicon active layers with crystallizing metal agent introduced only in the source/drain regions'
[patent_app_type] => 1
[patent_app_number] => 9/286104
[patent_app_country] => US
[patent_app_date] => 1999-04-02
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[pdf_file] => patents/06/242/06242779.pdf
[firstpage_image] =>[orig_patent_app_number] => 286104
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/286104 | Selective silicide thin-film transistor having polysilicon active layers with crystallizing metal agent introduced only in the source/drain regions | Apr 1, 1999 | Issued |
Array
(
[id] => 1375153
[patent_doc_number] => 06566756
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[patent_issue_date] => 2003-05-20
[patent_title] => 'Semiconductor device with porous interlayer film of a range of average diameter having partially closed holes'
[patent_app_type] => B1
[patent_app_number] => 09/280868
[patent_app_country] => US
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[pdf_file] => patents/06/566/06566756.pdf
[firstpage_image] =>[orig_patent_app_number] => 09280868
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/280868 | Semiconductor device with porous interlayer film of a range of average diameter having partially closed holes | Mar 28, 1999 | Issued |
Array
(
[id] => 4278143
[patent_doc_number] => 06323542
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument'
[patent_app_type] => 1
[patent_app_number] => 9/142856
[patent_app_country] => US
[patent_app_date] => 1999-03-26
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[firstpage_image] =>[orig_patent_app_number] => 142856
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/142856 | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument | Mar 25, 1999 | Issued |
Array
(
[id] => 4190285
[patent_doc_number] => 06160277
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-12
[patent_title] => 'Field effect transistor assemblies and transistor gate block stacks'
[patent_app_type] => 1
[patent_app_number] => 9/273080
[patent_app_country] => US
[patent_app_date] => 1999-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[firstpage_image] =>[orig_patent_app_number] => 273080
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/273080 | Field effect transistor assemblies and transistor gate block stacks | Mar 18, 1999 | Issued |
Array
(
[id] => 4292418
[patent_doc_number] => 06268630
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[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications'
[patent_app_type] => 1
[patent_app_number] => 9/270374
[patent_app_country] => US
[patent_app_date] => 1999-03-16
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[patent_drawing_sheets_cnt] => 7
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[firstpage_image] =>[orig_patent_app_number] => 270374
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/270374 | Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications | Mar 15, 1999 | Issued |
Array
(
[id] => 7643558
[patent_doc_number] => 06429483
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[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Semiconductor device and method for forming the same'
[patent_app_type] => B1
[patent_app_number] => 09/266864
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/266864 | Semiconductor device and method for forming the same | Mar 11, 1999 | Issued |
Array
(
[id] => 4301473
[patent_doc_number] => 06198150
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-06
[patent_title] => 'Integrated circuit with deep trench having multiple slopes'
[patent_app_type] => 1
[patent_app_number] => 9/266066
[patent_app_country] => US
[patent_app_date] => 1999-03-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/266066 | Integrated circuit with deep trench having multiple slopes | Mar 9, 1999 | Issued |
Array
(
[id] => 1522248
[patent_doc_number] => 06414353
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[patent_title] => 'TFT with partially depleted body'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/265697 | TFT with partially depleted body | Mar 9, 1999 | Issued |
Array
(
[id] => 4265878
[patent_doc_number] => 06259137
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[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Defect induced buried oxide (DIBOX) for throughput SOI'
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[patent_app_number] => 9/264973
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/264973 | Defect induced buried oxide (DIBOX) for throughput SOI | Mar 8, 1999 | Issued |
Array
(
[id] => 4423624
[patent_doc_number] => 06177707
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[patent_issue_date] => 2001-01-23
[patent_title] => 'Semiconductor device comprising a glass supporting body onto which a substrate with semiconductor elements and a metalization is attached by means of an adhesive'
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Array
(
[id] => 6475878
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[patent_title] => 'DRAM TECHNOLOGY COMPATIBLE NON VOLATILE MEMORY CELLS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/259493 | DRAM technology compatible non volatile memory cells with capacitors connected to the gates of the transistors | Feb 25, 1999 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/258563 | Metal wire fuse structure with cavity | Feb 25, 1999 | Issued |
Array
(
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Array
(
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Array
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Array
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