Fetsum Abraham

Array ( [id] => 4324719 [patent_doc_number] => 06249027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Partially depleted SOI device having a dedicated single body bias means' [patent_app_type] => 1 [patent_app_number] => 9/092974 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2068 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249027.pdf [firstpage_image] =>[orig_patent_app_number] => 092974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161169 [patent_doc_number] => 06104041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Switching circuitry layout for an active matrix electroluminescent display pixel with each pixel provided with the transistors' [patent_app_type] => 1 [patent_app_number] => 9/087570 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 5064 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104041.pdf [firstpage_image] =>[orig_patent_app_number] => 087570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4111401 [patent_doc_number] => 06023088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Semiconductor device formed on an insulator and having a damaged portion at the interface between the insulator and the active layer' [patent_app_type] => 1 [patent_app_number] => 9/085016 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2515 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023088.pdf [firstpage_image] =>[orig_patent_app_number] => 085016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3946959 [patent_doc_number] => 05981972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Actived matrix substrate having a transistor with multi-layered ohmic contact' [patent_app_type] => 1 [patent_app_number] => 9/079149 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5455 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981972.pdf [firstpage_image] =>[orig_patent_app_number] => 079149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3980253 [patent_doc_number] => 05917199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Solid state imager including TFTS with variably doped contact layer system for reducing TFT leakage current and increasing mobility and method of making same' [patent_app_type] => 1 [patent_app_number] => 9/079225 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917199.pdf [firstpage_image] =>[orig_patent_app_number] => 079225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4136780 [patent_doc_number] => 06034388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Depleted polysilicon circuit element and method for producing the same' [patent_app_type] => 1 [patent_app_number] => 9/079846 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 49 [patent_no_of_words] => 9534 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034388.pdf [firstpage_image] =>[orig_patent_app_number] => 079846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4265592 [patent_doc_number] => 06259119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Liquid crystal display and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/079896 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5530 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259119.pdf [firstpage_image] =>[orig_patent_app_number] => 079896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4123114 [patent_doc_number] => 06072193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Thin-film transistor and semiconductor device using thin-film transistors' [patent_app_type] => 1 [patent_app_number] => 9/079156 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 43 [patent_no_of_words] => 10467 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072193.pdf [firstpage_image] =>[orig_patent_app_number] => 079156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424581 [patent_doc_number] => 06225642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Buried channel vertical double diffusion MOS device' [patent_app_type] => 1 [patent_app_number] => 9/076363 [patent_app_country] => US [patent_app_date] => 1998-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1804 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225642.pdf [firstpage_image] =>[orig_patent_app_number] => 076363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4101217 [patent_doc_number] => 06097037 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Thin film transistor having a continuous crystallized layer including the channel and portions of source and drain regions' [patent_app_type] => 1 [patent_app_number] => 9/074606 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 4175 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097037.pdf [firstpage_image] =>[orig_patent_app_number] => 074606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4274888 [patent_doc_number] => 06307226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Contact openings to electronic components having recessed sidewall structures' [patent_app_type] => 1 [patent_app_number] => 9/062383 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3275 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307226.pdf [firstpage_image] =>[orig_patent_app_number] => 062383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3944501 [patent_doc_number] => 05973383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'High temperature ZrN and HfN IR scene projector pixels' [patent_app_type] => 1 [patent_app_number] => 9/057734 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3701 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973383.pdf [firstpage_image] =>[orig_patent_app_number] => 057734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373205 [patent_doc_number] => 06274908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Semiconductor device having input-output protection circuit' [patent_app_type] => 1 [patent_app_number] => 9/056634 [patent_app_country] => US [patent_app_date] => 1998-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 16228 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274908.pdf [firstpage_image] =>[orig_patent_app_number] => 056634 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4301224 [patent_doc_number] => 06198134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor device having a common substrate bias' [patent_app_type] => 1 [patent_app_number] => 9/056616 [patent_app_country] => US [patent_app_date] => 1998-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 90 [patent_no_of_words] => 12115 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198134.pdf [firstpage_image] =>[orig_patent_app_number] => 056616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309599 [patent_doc_number] => 06188111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Dual gate semiconductor device for shortening channel length' [patent_app_type] => 1 [patent_app_number] => 9/052157 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7098 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188111.pdf [firstpage_image] =>[orig_patent_app_number] => 052157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4163108 [patent_doc_number] => 06114731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Low capacitance ESD structure having a source inside a well and the bottom portion of the drain inside a substrate' [patent_app_type] => 1 [patent_app_number] => 9/049375 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114731.pdf [firstpage_image] =>[orig_patent_app_number] => 049375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3953283 [patent_doc_number] => 05977559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Thin-film transistor having a catalyst element in its active regions' [patent_app_type] => 1 [patent_app_number] => 9/048014 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977559.pdf [firstpage_image] =>[orig_patent_app_number] => 048014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4190503 [patent_doc_number] => 06160291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'SOI-MOS field effect transistor with improved source/drain structure' [patent_app_type] => 1 [patent_app_number] => 9/047504 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 36 [patent_no_of_words] => 35736 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160291.pdf [firstpage_image] =>[orig_patent_app_number] => 047504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4151695 [patent_doc_number] => 06064074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Semiconductor cathode and electron tube comprising a semiconductor cathode' [patent_app_type] => 1 [patent_app_number] => 9/046035 [patent_app_country] => US [patent_app_date] => 1998-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3203 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064074.pdf [firstpage_image] =>[orig_patent_app_number] => 046035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4277019 [patent_doc_number] => 06246092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'High breakdown voltage MOS semiconductor apparatus' [patent_app_type] => 1 [patent_app_number] => 9/042544 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 9877 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/246/06246092.pdf [firstpage_image] =>[orig_patent_app_number] => 042544 [rel_patent_id] =>[rel_patent_doc_number] =>)