| Application number | Title of the application | Filing Date | Status |
|---|
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[patent_issue_date] => 2001-08-07
[patent_title] => 'Voltage controlled resistance modulation for single event upset immunity'
[patent_app_type] => 1
[patent_app_number] => 8/999346
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Array
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[patent_doc_number] => 06124602
[patent_country] => US
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[patent_issue_date] => 2000-09-26
[patent_title] => 'Semiconductor circuit having a crystal growth in an active layer where a specific distance is established between a selected portion and where the growth starts to the active layer of the circuit'
[patent_app_type] => 1
[patent_app_number] => 8/998969
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[firstpage_image] =>[orig_patent_app_number] => 998969
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Array
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[patent_doc_number] => 06075257
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-13
[patent_title] => 'Thin film transistor substrate for a liquid crystal display having a silicide prevention insulating layer in the electrode structure'
[patent_app_type] => 1
[patent_app_number] => 8/996824
[patent_app_country] => US
[patent_app_date] => 1997-12-23
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Array
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[id] => 4091560
[patent_doc_number] => 06018180
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[patent_kind] => NA
[patent_issue_date] => 2000-01-25
[patent_title] => 'Transistor formation with LI overetch immunity'
[patent_app_type] => 1
[patent_app_number] => 8/996648
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[patent_app_date] => 1997-12-23
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Array
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[patent_kind] => NA
[patent_issue_date] => 2000-03-14
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[patent_app_number] => 8/996250
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Array
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[id] => 3953879
[patent_doc_number] => 05977602
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[patent_issue_date] => 1999-11-02
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| 08/994355 | SILICON-ON-INSULATOR CONFIGURATION WHICH IS COMPATIBLE WITH BULK CMOS ARCHITECTURE | Dec 18, 1997 | Abandoned |
Array
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[id] => 4376287
[patent_doc_number] => 06288414
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[patent_issue_date] => 2001-09-11
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[patent_app_number] => 8/993195
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[patent_app_date] => 1997-12-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/993195 | Liquid crystal display and a double layered metal contact | Dec 17, 1997 | Issued |
Array
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[id] => 4364408
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[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Semiconductor device with field shield electrode'
[patent_app_type] => 1
[patent_app_number] => 8/990285
[patent_app_country] => US
[patent_app_date] => 1997-12-15
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[firstpage_image] =>[orig_patent_app_number] => 990285
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990285 | Semiconductor device with field shield electrode | Dec 14, 1997 | Issued |
Array
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[patent_title] => 'Trench isolation of a CMOS structure'
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[patent_app_number] => 8/987226
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/987226 | Trench isolation of a CMOS structure | Dec 8, 1997 | Issued |
Array
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[patent_kind] => NA
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[patent_app_type] => 1
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[patent_issue_date] => 2000-05-30
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Array
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[patent_issue_date] => 2000-02-01
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Array
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Array
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[id] => 4294096
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[patent_issue_date] => 2001-04-03
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[patent_app_type] => 1
[patent_app_number] => 8/976963
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| 08/972806 | PROTECTIVE LINER FOR ISOLATION TRENCH SIDE WALLS AND METHOD | Nov 18, 1997 | Abandoned |
Array
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Array
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