Search

Fetsum Abraham

Examiner (ID: 18739)

Most Active Art Unit
2826
Art Unit(s)
2508, 2515, 2818, 2811, 2826, 2825
Total Applications
1055
Issued Applications
981
Pending Applications
32
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14903685 [patent_doc_number] => 20190295608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => Power Management Integrated Circuit with Dual Power Feed [patent_app_type] => utility [patent_app_number] => 16/438311 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16438311 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/438311
Power management integrated circuit with dual power feed Jun 10, 2019 Issued
Array ( [id] => 16509082 [patent_doc_number] => 20200388338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-10 [patent_title] => ROW DEPENDENT SENSING IN NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/432142 [patent_app_country] => US [patent_app_date] => 2019-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16432142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/432142
Row dependent sensing in nonvolatile memory Jun 4, 2019 Issued
Array ( [id] => 15219215 [patent_doc_number] => 20190372294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => APPARATUS AND METHOD FOR WIRE PREPARATION [patent_app_type] => utility [patent_app_number] => 16/430996 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430996 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430996
APPARATUS AND METHOD FOR WIRE PREPARATION Jun 3, 2019 Abandoned
Array ( [id] => 16323969 [patent_doc_number] => 10783939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-22 [patent_title] => Training of communication interfaces on printed circuit board [patent_app_type] => utility [patent_app_number] => 16/430154 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430154 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430154
Training of communication interfaces on printed circuit board Jun 2, 2019 Issued
Array ( [id] => 16637772 [patent_doc_number] => 10916286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Assisted write method for MRAM testing and field applications [patent_app_type] => utility [patent_app_number] => 16/428551 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 9324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16428551 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/428551
Assisted write method for MRAM testing and field applications May 30, 2019 Issued
Array ( [id] => 15822611 [patent_doc_number] => 10636499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/422112 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422112 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/422112
Semiconductor device May 23, 2019 Issued
Array ( [id] => 16966392 [patent_doc_number] => 20210217891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/054926 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17054926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/054926
Semiconductor device May 22, 2019 Issued
Array ( [id] => 15905509 [patent_doc_number] => 20200152275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => DEVICE AND METHOD FOR INITIALIZING CHANNEL IN NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/420850 [patent_app_country] => US [patent_app_date] => 2019-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16420850 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/420850
Device and method for initializing channel in nonvolatile memory device May 22, 2019 Issued
Array ( [id] => 15199805 [patent_doc_number] => 10497403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Power delivery circuitry [patent_app_type] => utility [patent_app_number] => 16/411899 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5240 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411899 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411899
Power delivery circuitry May 13, 2019 Issued
Array ( [id] => 15687491 [patent_doc_number] => 20200098409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => MAGNETIC RANDOM ACCESS MEMORY (MRAM) INTEGRATION [patent_app_type] => utility [patent_app_number] => 16/404549 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404549
MAGNETIC RANDOM ACCESS MEMORY (MRAM) INTEGRATION May 5, 2019 Abandoned
Array ( [id] => 14784361 [patent_doc_number] => 20190267078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SRAM Arrays and Methods of Manufacturing Same [patent_app_type] => utility [patent_app_number] => 16/404476 [patent_app_country] => US [patent_app_date] => 2019-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404476 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404476
SRAM arrays and methods of manufacturing same May 5, 2019 Issued
Array ( [id] => 16308473 [patent_doc_number] => 10777278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Non-volatile memory device and erasing method of the same [patent_app_type] => utility [patent_app_number] => 16/401877 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 14745 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401877 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/401877
Non-volatile memory device and erasing method of the same May 1, 2019 Issued
Array ( [id] => 15791057 [patent_doc_number] => 10629257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => SRAM with error correction in retention mode [patent_app_type] => utility [patent_app_number] => 16/399261 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399261 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399261
SRAM with error correction in retention mode Apr 29, 2019 Issued
Array ( [id] => 16424813 [patent_doc_number] => 20200350011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => SUB-WORD LINE DRIVER CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/399197 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16399197 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/399197
Sub-word line driver circuit Apr 29, 2019 Issued
Array ( [id] => 15154467 [patent_doc_number] => 20190355711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => Integrated Assemblies and Methods of Forming Integrated Assemblies [patent_app_type] => utility [patent_app_number] => 16/398433 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16398433 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/398433
Integrated assemblies and methods of forming integrated assemblies Apr 29, 2019 Issued
Array ( [id] => 15274563 [patent_doc_number] => 20190386016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/400013 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400013 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/400013
Non-volatile memory device Apr 29, 2019 Issued
Array ( [id] => 18205198 [patent_doc_number] => 11587600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Address/command chip controlled data chip address sequencing for a distributed memory buffer system [patent_app_type] => utility [patent_app_number] => 16/397154 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397154 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397154
Address/command chip controlled data chip address sequencing for a distributed memory buffer system Apr 28, 2019 Issued
Array ( [id] => 15472911 [patent_doc_number] => 10552333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Data storage device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/395141 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6228 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/395141
Data storage device and operating method thereof Apr 24, 2019 Issued
Array ( [id] => 14721889 [patent_doc_number] => 20190252008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => POWER SWITCH CONTROL FOR DUAL POWER SUPPLY [patent_app_type] => utility [patent_app_number] => 16/391986 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16391986 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/391986
Power switch control for dual power supply Apr 22, 2019 Issued
Array ( [id] => 16308458 [patent_doc_number] => 10777263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-15 [patent_title] => Josephson memory and logic circuits using quasi-long-junction interconnect [patent_app_type] => utility [patent_app_number] => 16/392330 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 40 [patent_no_of_words] => 7269 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16392330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/392330
Josephson memory and logic circuits using quasi-long-junction interconnect Apr 22, 2019 Issued
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