Fetsum Abraham

Array ( [id] => 13861793 [patent_doc_number] => 10192619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Methods for programming 1-R resistive change element arrays [patent_app_type] => utility [patent_app_number] => 15/657447 [patent_app_country] => US [patent_app_date] => 2017-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 46 [patent_no_of_words] => 33991 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15657447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12453822 [patent_doc_number] => 09983805 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-29 [patent_title] => Memory management method, memory control circuit unit and memory storage apparatus [patent_app_type] => utility [patent_app_number] => 15/655895 [patent_app_country] => US [patent_app_date] => 2017-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15655895 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13111515 [patent_doc_number] => 10074415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Boosting a digit line voltage for a write operation [patent_app_type] => utility [patent_app_number] => 15/645128 [patent_app_country] => US [patent_app_date] => 2017-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 13669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15645128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13797449 [patent_doc_number] => 20190012263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => Device and Method for Implementing Save Operation of Persistent Memory [patent_app_type] => utility [patent_app_number] => 15/644475 [patent_app_country] => US [patent_app_date] => 2017-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15644475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12989341 [patent_doc_number] => 20170345506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => METHODS OF OPERATING MEMORY UNDER ERASE CONDITIONS [patent_app_type] => utility [patent_app_number] => 15/638718 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13187671 [patent_doc_number] => 10109361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-23 [patent_title] => Coarse pass and fine pass multi-level NVM programming [patent_app_type] => utility [patent_app_number] => 15/637481 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7505 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15637481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12095306 [patent_doc_number] => 20170352398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'POWER REDUCTION FOR A SENSING OPERATION OF A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 15/636344 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16006 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11990066 [patent_doc_number] => 20170294221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'TRANSISTOR GAIN CELL WITH FEEDBACK' [patent_app_type] => utility [patent_app_number] => 15/632555 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13501 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632555 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12195339 [patent_doc_number] => 09899072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors' [patent_app_type] => utility [patent_app_number] => 15/631317 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13767101 [patent_doc_number] => 10175892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-08 [patent_title] => Adaptive read algorithm for a nonvolatile medium [patent_app_type] => utility [patent_app_number] => 15/632073 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13185 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13084701 [patent_doc_number] => 10062421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Memory controller with staggered request signal output [patent_app_type] => utility [patent_app_number] => 15/626097 [patent_app_country] => US [patent_app_date] => 2017-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19198881 [patent_doc_number] => 11996129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Semiconductor circuits and devices based on low-energy consumption semiconductor structures exhibiting multi-valued magnetoelectric spin hall effect [patent_app_type] => utility [patent_app_number] => 16/308337 [patent_app_country] => US [patent_app_date] => 2017-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 9854 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16308337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12550935 [patent_doc_number] => 10013194 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-03 [patent_title] => Handling thermal shutdown for memory devices [patent_app_type] => utility [patent_app_number] => 15/611958 [patent_app_country] => US [patent_app_date] => 2017-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5907 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15611958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13973779 [patent_doc_number] => 10216242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Power sequencing for embedded flash memory devices [patent_app_type] => utility [patent_app_number] => 15/610612 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4309 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12334236 [patent_doc_number] => 09947412 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-17 [patent_title] => Data writing method, memory control circuit unit and memory storage apparatus [patent_app_type] => utility [patent_app_number] => 15/603427 [patent_app_country] => US [patent_app_date] => 2017-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8783 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12395631 [patent_doc_number] => 09966129 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-08 [patent_title] => Controller and control method for dynamic random access memory [patent_app_type] => utility [patent_app_number] => 15/599859 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599859 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13098643 [patent_doc_number] => 10068664 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-04 [patent_title] => Column repair in memory [patent_app_type] => utility [patent_app_number] => 15/600409 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11105 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14175923 [patent_doc_number] => 10261977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Resistive memory accelerator [patent_app_type] => utility [patent_app_number] => 15/587024 [patent_app_country] => US [patent_app_date] => 2017-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8341 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13185713 [patent_doc_number] => 10108376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-23 [patent_title] => Memory initialization [patent_app_type] => utility [patent_app_number] => 15/587294 [patent_app_country] => US [patent_app_date] => 2017-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587294 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12249930 [patent_doc_number] => 09922711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating' [patent_app_type] => utility [patent_app_number] => 15/499519 [patent_app_country] => US [patent_app_date] => 2017-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 75 [patent_no_of_words] => 23790 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15499519 [rel_patent_id] =>[rel_patent_doc_number] =>)