Search

Fetsum Abraham

Examiner (ID: 18739)

Most Active Art Unit
2826
Art Unit(s)
2508, 2515, 2818, 2811, 2826, 2825
Total Applications
1055
Issued Applications
981
Pending Applications
32
Abandoned Applications
42

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19084872 [patent_doc_number] => 20240111673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => MEMORY DEVICE INTERFACE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/537357 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537357 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537357
Memory device interface and method Dec 11, 2023 Issued
Array ( [id] => 19073329 [patent_doc_number] => 20240107755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => NON-VOLATILE MEMORY (NVM) CELL STRUCTURE TO INCREASE RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/534818 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534818 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534818
Non-volatile memory (NVM) cell structure to increase reliability Dec 10, 2023 Issued
Array ( [id] => 19100760 [patent_doc_number] => 20240119988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => DELAY CONTROL CIRCUIT, DELAY CONTROL METHOD AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/533165 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533165
Delay control circuit, delay control method and memory Dec 6, 2023 Issued
Array ( [id] => 19935095 [patent_doc_number] => 12308303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Integrated circuit die with memory macro including through-silicon via and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/524668 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 7567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524668
Integrated circuit die with memory macro including through-silicon via and method of forming the same Nov 29, 2023 Issued
Array ( [id] => 20538566 [patent_doc_number] => 12555645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Systems and methods to perform automatic test pattern generation on multiple memory units in parallel [patent_app_type] => utility [patent_app_number] => 18/524526 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524526 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524526
Systems and methods to perform automatic test pattern generation on multiple memory units in parallel Nov 29, 2023 Issued
Array ( [id] => 20416672 [patent_doc_number] => 12499962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Counter-based sense amplifier method for memory cells [patent_app_type] => utility [patent_app_number] => 18/521891 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521891 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/521891
Counter-based sense amplifier method for memory cells Nov 27, 2023 Issued
Array ( [id] => 20258852 [patent_doc_number] => 12431215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Dynamic read calibration [patent_app_type] => utility [patent_app_number] => 18/519248 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519248 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519248
Dynamic read calibration Nov 26, 2023 Issued
Array ( [id] => 19646220 [patent_doc_number] => 20240420740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/517970 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18517970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/517970
Memory device and method of manufacturing the same Nov 21, 2023 Issued
Array ( [id] => 19382954 [patent_doc_number] => 20240272824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SYSTEM AND METHOD OF PERFORMING A READ OPERATION [patent_app_type] => utility [patent_app_number] => 18/518426 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518426
System and method of performing a read operation Nov 21, 2023 Issued
Array ( [id] => 19160849 [patent_doc_number] => 20240153556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => MATCHING PATTERNS IN MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 18/515692 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515692 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515692
Matching patterns in memory arrays Nov 20, 2023 Issued
Array ( [id] => 19057185 [patent_doc_number] => 20240099154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MAGNETORESISTIVE RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 18/515273 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515273 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515273
Magnetoresistive random access memory Nov 20, 2023 Issued
Array ( [id] => 20027163 [patent_doc_number] => 20250165385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SENSE TIME SEPARATION IN FOGGY-FINE PROGRAM TO IMPROVE OPTIMAL VT WIDTH [patent_app_type] => utility [patent_app_number] => 18/510857 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18510857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/510857
Sense time separation in foggy-fine program to improve optimal VT width Nov 15, 2023 Issued
Array ( [id] => 19335335 [patent_doc_number] => 20240249765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => BUFFER CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP AND MEMORY CHIP [patent_app_type] => utility [patent_app_number] => 18/509188 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509188 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/509188
Buffer chip, and semiconductor package including buffer chip and memory chip Nov 13, 2023 Issued
Array ( [id] => 19205848 [patent_doc_number] => 20240177747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT [patent_app_type] => utility [patent_app_number] => 18/388680 [patent_app_country] => US [patent_app_date] => 2023-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18388680 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/388680
Memory controller with staggered request signal output Nov 9, 2023 Issued
Array ( [id] => 19174377 [patent_doc_number] => 20240160351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => APPARATUSES AND METHODS FOR SEPARATE WRITE ENABLE FOR SINGLE-PASS ACCESS OF DATA, METADATA, AND PARITY INFORMATION [patent_app_type] => utility [patent_app_number] => 18/504362 [patent_app_country] => US [patent_app_date] => 2023-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504362 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/504362
APPARATUSES AND METHODS FOR SEPARATE WRITE ENABLE FOR SINGLE-PASS ACCESS OF DATA, METADATA, AND PARITY INFORMATION Nov 7, 2023 Pending
Array ( [id] => 20481812 [patent_doc_number] => 12530287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Read disturb tracking among multiple erase blocks coupled to a same string [patent_app_type] => utility [patent_app_number] => 18/386760 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/386760
Read disturb tracking among multiple erase blocks coupled to a same string Nov 2, 2023 Issued
Array ( [id] => 20481813 [patent_doc_number] => 12530288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Read disturb tracking among multiple erase blocks coupled to a same string [patent_app_type] => utility [patent_app_number] => 18/386783 [patent_app_country] => US [patent_app_date] => 2023-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386783 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/386783
Read disturb tracking among multiple erase blocks coupled to a same string Nov 2, 2023 Issued
Array ( [id] => 18977392 [patent_doc_number] => 20240057484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => MEMORY CELLS BASED ON SUPERCONDUCTING AND MAGNETIC MATERIALS AND METHODS OF THEIR CONTROL IN ARRAYS [patent_app_type] => utility [patent_app_number] => 18/492511 [patent_app_country] => US [patent_app_date] => 2023-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18492511 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/492511
Memory cells based on superconducting and magnetic materials and methods of their control in arrays Oct 22, 2023 Issued
Array ( [id] => 20758853 [patent_doc_number] => 12651630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Tracking scheme circuit of memory device and methods for operating the same [patent_app_type] => utility [patent_app_number] => 18/480762 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18480762 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/480762
Tracking scheme circuit of memory device and methods for operating the same Oct 3, 2023 Issued
Array ( [id] => 20611028 [patent_doc_number] => 12586632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Signal receiver, data receiver and data latch thereof [patent_app_type] => utility [patent_app_number] => 18/481224 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481224 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/481224
Signal receiver, data receiver and data latch thereof Oct 3, 2023 Issued
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