Search

Fiona Powers

Examiner (ID: 3954)

Most Active Art Unit
1626
Art Unit(s)
2899, 1201, 1613, 1626
Total Applications
2100
Issued Applications
1653
Pending Applications
85
Abandoned Applications
362

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20182134 [patent_doc_number] => 20250266092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => BLOCK SELECTION CIRCUIT CONTROLLING SERIES-CONNECTED PASS TRANSISTORS USING SHARED SWITCH CIRCUIT AND FLASH MEMORY INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/975798 [patent_app_country] => US [patent_app_date] => 2024-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18975798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/975798
Block selection circuit controlling series--connected pass transistors using shared switch circuit and flash memory including the same Dec 9, 2024 Issued
Array ( [id] => 19711118 [patent_doc_number] => 20250021260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/899647 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18899647 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/899647
MEMORY SYSTEM Sep 26, 2024 Pending
Array ( [id] => 19687690 [patent_doc_number] => 20250006235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MODIFICATION OF A COMMAND TIMING PATTERN [patent_app_type] => utility [patent_app_number] => 18/882478 [patent_app_country] => US [patent_app_date] => 2024-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882478 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/882478
MODIFICATION OF A COMMAND TIMING PATTERN Sep 10, 2024 Pending
Array ( [id] => 19820699 [patent_doc_number] => 20250078906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => MEMORY DEVICE AND MEMORY MODULE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/818007 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18818007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/818007
MEMORY DEVICE AND MEMORY MODULE INCLUDING THE SAME Aug 27, 2024 Pending
Array ( [id] => 19646245 [patent_doc_number] => 20240420765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/818527 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 419 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18818527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/818527
SEMICONDUCTOR STORAGE DEVICE Aug 27, 2024 Pending
Array ( [id] => 19803743 [patent_doc_number] => 20250069668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => MEMORY DEVICE FOR PROGRAM DISTURBANCE SUPPRESSION AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/814030 [patent_app_country] => US [patent_app_date] => 2024-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814030 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/814030
MEMORY DEVICE FOR PROGRAM DISTURBANCE SUPPRESSION AND PROGRAMMING METHOD THEREOF Aug 22, 2024 Pending
Array ( [id] => 19773138 [patent_doc_number] => 20250054564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/795818 [patent_app_country] => US [patent_app_date] => 2024-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18795818 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/795818
MEMORY SYSTEM Aug 5, 2024 Pending
Array ( [id] => 20514476 [patent_doc_number] => 20260038578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => SENSE AMPLIFIER BALANCING COMPONENT [patent_app_type] => utility [patent_app_number] => 18/788948 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788948 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788948
SENSE AMPLIFIER BALANCING COMPONENT Jul 29, 2024 Pending
Array ( [id] => 19589393 [patent_doc_number] => 20240386950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => READ AND WRITE ENHANCEMENTS FOR ARRAYS OF SUPERCONDUCTING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/788480 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788480 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788480
READ AND WRITE ENHANCEMENTS FOR ARRAYS OF SUPERCONDUCTING MEMORY CELLS Jul 29, 2024 Pending
Array ( [id] => 20352521 [patent_doc_number] => 20250349373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/783124 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783124
MEMORY DEVICE AND OPERATION METHOD THEREOF Jul 23, 2024 Pending
Array ( [id] => 20474966 [patent_doc_number] => 20260017187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => MEMORY DEVICE AND OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/781491 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781491 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781491
MEMORY DEVICE AND OPERATION THEREOF Jul 22, 2024 Pending
Array ( [id] => 19559631 [patent_doc_number] => 20240371423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/778659 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778659 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/778659
CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES Jul 18, 2024 Pending
Array ( [id] => 19559636 [patent_doc_number] => 20240371428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => POWER MODE WAKE-UP FOR MEMORY ON DIFFERENT POWER DOMAINS [patent_app_type] => utility [patent_app_number] => 18/772721 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772721 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772721
POWER MODE WAKE-UP FOR MEMORY ON DIFFERENT POWER DOMAINS Jul 14, 2024 Pending
Array ( [id] => 20367083 [patent_doc_number] => 20250356895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => MRAM CIRCUIT AND LAYOUT [patent_app_type] => utility [patent_app_number] => 18/752801 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752801 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752801
MRAM circuit and layout Jun 24, 2024 Issued
Array ( [id] => 19850394 [patent_doc_number] => 20250095745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => BLOCK SELECTION CIRCUIT CONTROLLING SERIES CONNECTED PASS TRANSISTORS AND FLASH MEMORY INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/677536 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677536 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677536
Block selection circuit controlling series connected pass transistors and flash memory including the same May 28, 2024 Issued
Array ( [id] => 19467657 [patent_doc_number] => 20240321327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => PRE-DECODER CIRCUITRY [patent_app_type] => utility [patent_app_number] => 18/677609 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677609 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677609
PRE-DECODER CIRCUITRY May 28, 2024 Pending
Array ( [id] => 20229150 [patent_doc_number] => 12417804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Low power management for sleep mode operation of a memory device [patent_app_type] => utility [patent_app_number] => 18/675997 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675997 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675997
Low power management for sleep mode operation of a memory device May 27, 2024 Issued
Array ( [id] => 20088542 [patent_doc_number] => 20250218478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/669931 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669931
Semiconductor memory devices and memory systems including the same May 20, 2024 Issued
Array ( [id] => 19435730 [patent_doc_number] => 20240304228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SYSTEMS AND METHODS FOR DUAL STANDBY MODES IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/668795 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/668795
Systems and methods for dual standby modes in memory May 19, 2024 Issued
Array ( [id] => 19917457 [patent_doc_number] => 12292826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Method for managing a memory apparatus [patent_app_type] => utility [patent_app_number] => 18/663114 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 9173 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663114 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663114
Method for managing a memory apparatus May 13, 2024 Issued
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