Fiona Powers

Array ( [id] => 17025212 [patent_doc_number] => 20210249084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => HIGH-VOLTAGE SHIFTER WITH REDUCED TRANSISTOR DEGRADATION [patent_app_type] => utility [patent_app_number] => 17/240358 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17240358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18088398 [patent_doc_number] => 11538537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Negative gate stress operation in multi-pass programming and memory device thereof [patent_app_type] => utility [patent_app_number] => 17/232059 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 16740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17847724 [patent_doc_number] => 11437108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-06 [patent_title] => Voltage bin calibration based on a temporary voltage shift offset [patent_app_type] => utility [patent_app_number] => 17/230786 [patent_app_country] => US [patent_app_date] => 2021-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 16449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16995169 [patent_doc_number] => 20210233589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/227820 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17878365 [patent_doc_number] => 11450386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Nonvolatile memory device performing two-way channel precharge [patent_app_type] => utility [patent_app_number] => 17/221833 [patent_app_country] => US [patent_app_date] => 2021-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 16356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17878344 [patent_doc_number] => 11450365 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Input/output circuit, operation method of the input/output circuit and data processing system including the input/output circuit [patent_app_type] => utility [patent_app_number] => 17/221312 [patent_app_country] => US [patent_app_date] => 2021-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5810 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17221312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17787600 [patent_doc_number] => 11410734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-09 [patent_title] => Voltage bin selection for blocks of a memory device after power up of the memory device [patent_app_type] => utility [patent_app_number] => 17/219498 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17219498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17558893 [patent_doc_number] => 11315612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Semiconductor storing apparatus and pre-charge method [patent_app_type] => utility [patent_app_number] => 17/216713 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216713 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17708266 [patent_doc_number] => 20220208274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MEMORY DEVICE INCLUDING VOLTAGE CONTROL FOR DIFUSSION REGIONS ASSOCIATED WITH MEMORY BLOCKS [patent_app_type] => utility [patent_app_number] => 17/217014 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19964637 [patent_doc_number] => 12334152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Simultaneous programming of multiple sub-blocks in NAND memory structures [patent_app_type] => utility [patent_app_number] => 17/212792 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18235774 [patent_doc_number] => 11600338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Memory device and method of operating the memory device [patent_app_type] => utility [patent_app_number] => 17/208711 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 14718 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17208711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16936090 [patent_doc_number] => 20210201979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => APPARATUSES AND METHODS TO PERFORM DUTY CYCLE ADJUSTMENT WITH BACK-BIAS VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/199207 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17402650 [patent_doc_number] => 20220044741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/198382 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17606927 [patent_doc_number] => 11335419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-17 [patent_title] => Erase technique for checking integrity of non-data word lines in memory device and corresponding firmware [patent_app_type] => utility [patent_app_number] => 17/197762 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 22384 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17438722 [patent_doc_number] => 11264061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Control method for memory device [patent_app_type] => utility [patent_app_number] => 17/197632 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4718 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17772182 [patent_doc_number] => 11404133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-02 [patent_title] => Valid translation unit count-based memory management [patent_app_type] => utility [patent_app_number] => 17/196629 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19740329 [patent_doc_number] => 12217165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Concurrent write and verify operations in an analog neural memory [patent_app_type] => utility [patent_app_number] => 17/190376 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 10281 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18363149 [patent_doc_number] => 20230144740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/918412 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17918412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16887360 [patent_doc_number] => 20210173557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => BANK TO BANK DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 17/178889 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17730571 [patent_doc_number] => 11386969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-12 [patent_title] => Method and system for improving word line data retention for memory blocks [patent_app_type] => utility [patent_app_number] => 17/176867 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 17176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176867 [rel_patent_id] =>[rel_patent_doc_number] =>)