Search

Fiona Powers

Examiner (ID: 3954)

Most Active Art Unit
1626
Art Unit(s)
2899, 1201, 1613, 1626
Total Applications
2100
Issued Applications
1653
Pending Applications
85
Abandoned Applications
362

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17606901 [patent_doc_number] => 11335393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Semiconductor device performing refresh operation in deep sleep mode [patent_app_type] => utility [patent_app_number] => 17/173048 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173048
Semiconductor device performing refresh operation in deep sleep mode Feb 9, 2021 Issued
Array ( [id] => 17416821 [patent_doc_number] => 20220051725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/173008 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173008
Memory device and method of operating the same Feb 9, 2021 Issued
Array ( [id] => 16856758 [patent_doc_number] => 20210157503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => APPARATUSES AND METHODS FOR PARTITIONED PARALLEL DATA MOVEMENT [patent_app_type] => utility [patent_app_number] => 17/170508 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170508
Apparatuses and methods for partitioned parallel data movement Feb 7, 2021 Issued
Array ( [id] => 17402641 [patent_doc_number] => 20220044732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/168778 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168778 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168778
Memory device and operating method thereof Feb 4, 2021 Issued
Array ( [id] => 17417777 [patent_doc_number] => 20220052681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => DRIVER AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/167553 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167553 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167553
Driver and method of operating the same Feb 3, 2021 Issued
Array ( [id] => 17107238 [patent_doc_number] => 11127463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Memory device and method of operation [patent_app_type] => utility [patent_app_number] => 17/166879 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 15686 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166879
Memory device and method of operation Feb 2, 2021 Issued
Array ( [id] => 16989566 [patent_doc_number] => 20210227986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => MULTI-STAGE MEMORY SENSING [patent_app_type] => utility [patent_app_number] => 17/165533 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165533
Multi-stage memory sensing Feb 1, 2021 Issued
Array ( [id] => 16873288 [patent_doc_number] => 20210166755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => NONVOLATILE MEMORY AND WRITING METHOD [patent_app_type] => utility [patent_app_number] => 17/154513 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154513 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/154513
Nonvolatile memory and writing method Jan 20, 2021 Issued
Array ( [id] => 17040396 [patent_doc_number] => 20210257032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/148591 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148591 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148591
Semiconductor device Jan 13, 2021 Issued
Array ( [id] => 17543908 [patent_doc_number] => 11309040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Managed NAND performance throttling [patent_app_type] => utility [patent_app_number] => 17/147222 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 23034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147222 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147222
Managed NAND performance throttling Jan 11, 2021 Issued
Array ( [id] => 17246818 [patent_doc_number] => 20210366563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => OTP MEMORY AND STORAGE DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/145636 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145636 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145636
OTP memory and storage device including the same Jan 10, 2021 Issued
Array ( [id] => 17024580 [patent_doc_number] => 20210248452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => MULTIPLY ACCUMULATE CIRCUIT FOR BINARY NEURAL NETWORK SYSTEM [patent_app_type] => utility [patent_app_number] => 17/141333 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141333 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141333
Multiply accumulate circuit for binary neural network system Jan 4, 2021 Issued
Array ( [id] => 19277096 [patent_doc_number] => 12027227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Low power management for sleep mode operation of a memory device [patent_app_type] => utility [patent_app_number] => 17/426963 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17426963 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/426963
Low power management for sleep mode operation of a memory device Dec 21, 2020 Issued
Array ( [id] => 17691870 [patent_doc_number] => 20220199163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SETTING AN INITIAL ERASE VOLTAGE USING FEEDBACK FROM PREVIOUS OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/127358 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127358 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127358
Setting an initial erase voltage using feedback from previous operations Dec 17, 2020 Issued
Array ( [id] => 17691894 [patent_doc_number] => 20220199187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => SMART SAMPLING FOR BLOCK FAMILY SCAN [patent_app_type] => utility [patent_app_number] => 17/125895 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125895 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125895
Smart sampling for block family scan Dec 16, 2020 Issued
Array ( [id] => 17676404 [patent_doc_number] => 20220189571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => TRIMS CORRESPONDING TO PROGRAM/ERASE CYCLES [patent_app_type] => utility [patent_app_number] => 17/122758 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122758
Trims corresponding to program/erase cycles Dec 14, 2020 Issued
Array ( [id] => 16752275 [patent_doc_number] => 20210104287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => LAYOUT STRUCTURES OF MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/123039 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123039
Layout structures of memory array Dec 14, 2020 Issued
Array ( [id] => 17232137 [patent_doc_number] => 20210358694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => CAPACITOR, METHOD OF CONTROLLING THE SAME, AND TRANSISTOR INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/116097 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116097
Capacitor, method of controlling the same, and transistor including the same Dec 8, 2020 Issued
Array ( [id] => 17757985 [patent_doc_number] => 11398283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Analog peak power management for multi-die operations [patent_app_type] => utility [patent_app_number] => 17/116253 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116253 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116253
Analog peak power management for multi-die operations Dec 8, 2020 Issued
Array ( [id] => 17637931 [patent_doc_number] => 11348660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-31 [patent_title] => Semiconductor device performing loop-back test operation [patent_app_type] => utility [patent_app_number] => 17/105137 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2916 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105137
Semiconductor device performing loop-back test operation Nov 24, 2020 Issued
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