Search

Fiona Powers

Examiner (ID: 3954)

Most Active Art Unit
1626
Art Unit(s)
2899, 1201, 1613, 1626
Total Applications
2100
Issued Applications
1653
Pending Applications
85
Abandoned Applications
362

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17002354 [patent_doc_number] => 11081176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => 2T-1R architecture for resistive RAM [patent_app_type] => utility [patent_app_number] => 16/796428 [patent_app_country] => US [patent_app_date] => 2020-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 64 [patent_no_of_words] => 13000 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/796428
2T-1R architecture for resistive RAM Feb 19, 2020 Issued
Array ( [id] => 16802124 [patent_doc_number] => 10997068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-04 [patent_title] => Rapid SSD preconditioning [patent_app_type] => utility [patent_app_number] => 16/789026 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16789026 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/789026
Rapid SSD preconditioning Feb 11, 2020 Issued
Array ( [id] => 17016907 [patent_doc_number] => 11086546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => Preserve write for solid-state drives [patent_app_type] => utility [patent_app_number] => 16/746349 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746349
Preserve write for solid-state drives Jan 16, 2020 Issued
Array ( [id] => 16600258 [patent_doc_number] => 20210026789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => Method of Memory Time Division Control and Related Device [patent_app_type] => utility [patent_app_number] => 16/744202 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744202 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/744202
Method of memory time division control and related device Jan 15, 2020 Issued
Array ( [id] => 16544658 [patent_doc_number] => 20200411073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-31 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/728120 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728120 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728120
Memory device and method of operating the same Dec 26, 2019 Issued
Array ( [id] => 16332052 [patent_doc_number] => 20200303018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => MEMORY SYSTEM AND NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/727488 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727488 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727488
Memory system and nonvolatile memory Dec 25, 2019 Issued
Array ( [id] => 16834957 [patent_doc_number] => 11011215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-18 [patent_title] => Apparatus with an internal-operation management mechanism [patent_app_type] => utility [patent_app_number] => 16/721373 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7447 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721373
Apparatus with an internal-operation management mechanism Dec 18, 2019 Issued
Array ( [id] => 17699963 [patent_doc_number] => 11373695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Memory accessing with auto-precharge [patent_app_type] => utility [patent_app_number] => 16/719907 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 17055 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719907
Memory accessing with auto-precharge Dec 17, 2019 Issued
Array ( [id] => 16147675 [patent_doc_number] => 10706912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Memories configured to control discharge of a control gate voltage of a transistor connected between a data line and a common source [patent_app_type] => utility [patent_app_number] => 16/710006 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710006 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710006
Memories configured to control discharge of a control gate voltage of a transistor connected between a data line and a common source Dec 10, 2019 Issued
Array ( [id] => 16904534 [patent_doc_number] => 20210183450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => ERASE SUSPEND SCHEME IN A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/710526 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710526
Erase suspend scheme in a storage device Dec 10, 2019 Issued
Array ( [id] => 16699684 [patent_doc_number] => 10950292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-16 [patent_title] => Method and apparatus for mitigating row hammer attacks [patent_app_type] => utility [patent_app_number] => 16/710424 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6618 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16710424 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/710424
Method and apparatus for mitigating row hammer attacks Dec 10, 2019 Issued
Array ( [id] => 16752267 [patent_doc_number] => 20210104279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => SINGLE-GATE MULTIPLE-TIME PROGRAMMING NON-VOLATILE MEMORY ARRAY AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/708888 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16708888 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/708888
SINGLE-GATE MULTIPLE-TIME PROGRAMMING NON-VOLATILE MEMORY ARRAY AND OPERATING METHOD THEREOF Dec 9, 2019 Abandoned
Array ( [id] => 16738729 [patent_doc_number] => 10964390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-30 [patent_title] => Skip coding for fractional bit-per-cell NAND memories [patent_app_type] => utility [patent_app_number] => 16/709338 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5280 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709338 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/709338
Skip coding for fractional bit-per-cell NAND memories Dec 9, 2019 Issued
Array ( [id] => 16942985 [patent_doc_number] => 11055227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Controller and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/702795 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 9443 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16702795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/702795
Controller and operating method thereof Dec 3, 2019 Issued
Array ( [id] => 16192921 [patent_doc_number] => 20200233770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/696396 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696396
Memory system and operating method thereof Nov 25, 2019 Issued
Array ( [id] => 16928062 [patent_doc_number] => 11049551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Memory devices providing in situ computing using sequential transfer of row buffered data and related methods and circuits [patent_app_type] => utility [patent_app_number] => 16/682151 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7713 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682151
Memory devices providing in situ computing using sequential transfer of row buffered data and related methods and circuits Nov 12, 2019 Issued
Array ( [id] => 16810994 [patent_doc_number] => 20210133549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => CHARGE-SHARING COMPUTE-IN-MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/669855 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669855 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669855
Charge-sharing compute-in-memory system Oct 30, 2019 Issued
Array ( [id] => 16179105 [patent_doc_number] => 20200226073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => RANDOM CODE GENERATOR WITH NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/661012 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661012 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661012
Random code generator with non-volatile memory Oct 22, 2019 Issued
Array ( [id] => 16699683 [patent_doc_number] => 10950291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-16 [patent_title] => Apparatuses and methods to perform duty cycle adjustment with back-bias voltage [patent_app_type] => utility [patent_app_number] => 16/661784 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9157 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661784
Apparatuses and methods to perform duty cycle adjustment with back-bias voltage Oct 22, 2019 Issued
Array ( [id] => 16119187 [patent_doc_number] => 20200211616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => POWER CONTROL CIRCUIT, SEMICONDUCTOR APPARATUS INCLUDING THE SAME AND POWER CONTROL METHOD OF SEMICONDUCTOR APPARATUS [patent_app_type] => utility [patent_app_number] => 16/661342 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661342 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661342
Power control circuit, semiconductor apparatus including the same and power control method of semiconductor apparatus Oct 22, 2019 Issued
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