Search

Fiona Powers

Examiner (ID: 3954)

Most Active Art Unit
1626
Art Unit(s)
2899, 1201, 1613, 1626
Total Applications
2100
Issued Applications
1653
Pending Applications
85
Abandoned Applications
362

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17018193 [patent_doc_number] => 11087838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Voltage drivers with reduced power consumption during polarity transition [patent_app_type] => utility [patent_app_number] => 16/660594 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4215 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16660594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/660594
Voltage drivers with reduced power consumption during polarity transition Oct 21, 2019 Issued
Array ( [id] => 17062901 [patent_doc_number] => 11107510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions [patent_app_type] => utility [patent_app_number] => 16/657445 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657445
Memory bank power coordination including concurrently performing a memory operation in a selected number of memory regions Oct 17, 2019 Issued
Array ( [id] => 15459225 [patent_doc_number] => 20200042437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => METHOD FOR MANAGING A MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/596703 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596703 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596703
Method for managing a memory apparatus Oct 7, 2019 Issued
Array ( [id] => 15775209 [patent_doc_number] => 20200118622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => LINEARLY WEIGHT UPDATABLE CMOS SYNAPTIC ARRAY WITHOUT CELL LOCATION DEPENDENCE [patent_app_type] => utility [patent_app_number] => 16/592334 [patent_app_country] => US [patent_app_date] => 2019-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592334 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/592334
Linearly weight updatable CMOS synaptic array without cell location dependence Oct 2, 2019 Issued
Array ( [id] => 16447975 [patent_doc_number] => 10839906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => In memory computing (IMC) memory circuit having 6T cells [patent_app_type] => utility [patent_app_number] => 16/588140 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 15021 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588140 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588140
In memory computing (IMC) memory circuit having 6T cells Sep 29, 2019 Issued
Array ( [id] => 16653148 [patent_doc_number] => 10930339 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-23 [patent_title] => Voltage bitline high (VBLH) regulation for computer memory [patent_app_type] => utility [patent_app_number] => 16/587496 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587496 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587496
Voltage bitline high (VBLH) regulation for computer memory Sep 29, 2019 Issued
Array ( [id] => 16865619 [patent_doc_number] => 11024370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Static random access memory with write assist adjustment [patent_app_type] => utility [patent_app_number] => 16/587504 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587504 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587504
Static random access memory with write assist adjustment Sep 29, 2019 Issued
Array ( [id] => 16684158 [patent_doc_number] => 10943647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-09 [patent_title] => Bit-line mux driver with diode header for computer memory [patent_app_type] => utility [patent_app_number] => 16/587560 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587560 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587560
Bit-line mux driver with diode header for computer memory Sep 29, 2019 Issued
Array ( [id] => 15351151 [patent_doc_number] => 20200013467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATION [patent_app_type] => utility [patent_app_number] => 16/574669 [patent_app_country] => US [patent_app_date] => 2019-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574669 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/574669
Memory device and method of operation Sep 17, 2019 Issued
Array ( [id] => 16097923 [patent_doc_number] => 20200202948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/561454 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561454 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561454
Semiconductor memory device Sep 4, 2019 Issued
Array ( [id] => 17195874 [patent_doc_number] => 11164639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/561094 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 31 [patent_no_of_words] => 20448 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561094 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561094
Semiconductor memory device Sep 4, 2019 Issued
Array ( [id] => 15839977 [patent_doc_number] => 20200135271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/560472 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560472 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560472
Semiconductor memory device Sep 3, 2019 Issued
Array ( [id] => 16536263 [patent_doc_number] => 10878876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Apparatuses and methods for providing power for memory refresh operations [patent_app_type] => utility [patent_app_number] => 16/557948 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5195 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16557948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/557948
Apparatuses and methods for providing power for memory refresh operations Aug 29, 2019 Issued
Array ( [id] => 16130103 [patent_doc_number] => 10698812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Updating cache using two bloom filters [patent_app_type] => utility [patent_app_number] => 16/550613 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6086 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550613 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550613
Updating cache using two bloom filters Aug 25, 2019 Issued
Array ( [id] => 15461469 [patent_doc_number] => 20200043559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => MANAGED NAND PERFORMANCE THROTTLING [patent_app_type] => utility [patent_app_number] => 16/542963 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542963 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542963
Managed NAND performance throttling Aug 15, 2019 Issued
Array ( [id] => 16684157 [patent_doc_number] => 10943646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Memory device, driving method thereof, semiconductor device, electronic component, and electronic device [patent_app_type] => utility [patent_app_number] => 16/541239 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 55 [patent_no_of_words] => 15844 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541239
Memory device, driving method thereof, semiconductor device, electronic component, and electronic device Aug 14, 2019 Issued
Array ( [id] => 15214371 [patent_doc_number] => 20190369872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => BANK TO BANK DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 16/541764 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541764
Bank to bank data transfer Aug 14, 2019 Issued
Array ( [id] => 15184335 [patent_doc_number] => 20190362759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => APPARATUSES AND METHODS TO SELECTIVELY PERFORM LOGICAL OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/537775 [patent_app_country] => US [patent_app_date] => 2019-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537775 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537775
Apparatuses and methods to selectively perform logical operations Aug 11, 2019 Issued
Array ( [id] => 16339050 [patent_doc_number] => 10790017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Nonvolatile memory and writing method [patent_app_type] => utility [patent_app_number] => 16/529322 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 57 [patent_no_of_words] => 19452 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 735 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529322
Nonvolatile memory and writing method Jul 31, 2019 Issued
Array ( [id] => 15153837 [patent_doc_number] => 20190355396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => CONTROL METHOD FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/526589 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526589 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526589
CONTROL METHOD FOR MEMORY DEVICE Jul 29, 2019 Abandoned
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