Fiona Powers

Array ( [id] => 12895486 [patent_doc_number] => 20180190337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => GROUND REFERENCE SCHEME FOR A MEMORY CELL [patent_app_type] => utility [patent_app_number] => 15/855326 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14035965 [patent_doc_number] => 10229735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-12 [patent_title] => Block management for dynamic single-level cell buffers in storage devices [patent_app_type] => utility [patent_app_number] => 15/852928 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6587 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15852928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14151155 [patent_doc_number] => 10255961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Data storage in synthetic antiferromagnets included in magnetic tunnel junctions [patent_app_type] => utility [patent_app_number] => 15/851816 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 8780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15851816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14768665 [patent_doc_number] => 10395733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Forming structure and method for integrated circuit memory [patent_app_type] => utility [patent_app_number] => 15/850188 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7649 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14508859 [patent_doc_number] => 20190198084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => MANAGEMENT OF STROBE/CLOCK PHASE TOLERANCES DURING EXTENDED WRITE PREAMBLES [patent_app_type] => utility [patent_app_number] => 15/850744 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15108361 [patent_doc_number] => 10475510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Leakage compensation read method for memory device [patent_app_type] => utility [patent_app_number] => 15/850280 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6182 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15545201 [patent_doc_number] => 10572381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Updating cache using two bloom filters [patent_app_type] => utility [patent_app_number] => 15/841890 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5975 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13819759 [patent_doc_number] => 10186657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Three-terminal metastable symmetric zero-volt battery memristive device [patent_app_type] => utility [patent_app_number] => 15/832300 [patent_app_country] => US [patent_app_date] => 2017-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5001 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13471019 [patent_doc_number] => 20180287052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => MAGNETIC STRUCTURES INCLUDING FePd [patent_app_type] => utility [patent_app_number] => 15/829134 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10384 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12895489 [patent_doc_number] => 20180190338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => FERROELECTRIC-MODULATED SCHOTTKY NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 15/829004 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13214299 [patent_doc_number] => 10121524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-06 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/828974 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9688 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15828974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14888665 [patent_doc_number] => 10424379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Polarization-based configurable logic gate [patent_app_type] => utility [patent_app_number] => 15/829076 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8553 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12668155 [patent_doc_number] => 20180114551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => APPARATUSES AND METHODS TO SELECTIVELY PERFORM LOGICAL OPERATIONS [patent_app_type] => utility [patent_app_number] => 15/797759 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13131585 [patent_doc_number] => 10083730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-25 [patent_title] => Thermally-assisted spin transfer torque memory with improved bit error rate performance [patent_app_type] => utility [patent_app_number] => 15/794425 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11120 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12181432 [patent_doc_number] => 20180040368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'Methods of Programming Memory Devices' [patent_app_type] => utility [patent_app_number] => 15/783040 [patent_app_country] => US [patent_app_date] => 2017-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15783040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14643977 [patent_doc_number] => 10366736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => MTP-Thyristor memory cell circuits and methods of operation [patent_app_type] => utility [patent_app_number] => 15/698447 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 12985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12243023 [patent_doc_number] => 20180075886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'STORAGE DEVICE, METHOD FOR OPERATING STORAGE DEVICE, SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/695210 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13403 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13451307 [patent_doc_number] => 20180277196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => DOUBLE DATA RATE SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY AND OUTPUT DRIVING CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 15/695830 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13451351 [patent_doc_number] => 20180277218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/695470 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695470 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13434697 [patent_doc_number] => 20180268891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/695866 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695866 [rel_patent_id] =>[rel_patent_doc_number] =>)