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Fouzia Hye Solaiman

Examiner (ID: 5699)

Most Active Art Unit
2659
Art Unit(s)
2659
Total Applications
48
Issued Applications
4
Pending Applications
41
Abandoned Applications
3

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8166368 [patent_doc_number] => 20120104559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Semiconductor Device Having Island Type Support Patterns' [patent_app_type] => utility [patent_app_number] => 13/238408 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104559.pdf [firstpage_image] =>[orig_patent_app_number] => 13238408 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238408
Semiconductor Device Having Island Type Support Patterns Sep 20, 2011 Abandoned
Array ( [id] => 8462491 [patent_doc_number] => 20120267659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'LED PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/238048 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4968 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238048
LED PACKAGE STRUCTURE Sep 20, 2011 Abandoned
Array ( [id] => 8718019 [patent_doc_number] => 20130069236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'EFFICIENT SEMICONDUCTOR DEVICE CELL LAYOUT UTILIZING UNDERLYING LOCAL CONNECTIVE FEATURES' [patent_app_type] => utility [patent_app_number] => 13/238294 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13238294 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/238294
Efficient semiconductor device cell layout utilizing underlying local connective features Sep 20, 2011 Issued
Array ( [id] => 8717937 [patent_doc_number] => 20130069154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'SEMICONDUCTOR CHIP INTEGRATING HIGH AND LOW VOLTAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 13/237852 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237852 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237852
SEMICONDUCTOR CHIP INTEGRATING HIGH AND LOW VOLTAGE DEVICES Sep 19, 2011 Abandoned
Array ( [id] => 8720787 [patent_doc_number] => 20130072004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'METHOD OF INTEGRATING HIGH VOLTAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 13/237842 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4644 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237842 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237842
Method of integrating high voltage devices Sep 19, 2011 Issued
Array ( [id] => 8519739 [patent_doc_number] => 20120319147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'ORGANIC LIGHT EMITTING DIODE DISPLAY' [patent_app_type] => utility [patent_app_number] => 13/237877 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11396 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13237877 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/237877
Organic light emitting diode display Sep 19, 2011 Issued
Array ( [id] => 9818316 [patent_doc_number] => 08928105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Method and apparatus for thin film module with dotted interconnects and vias' [patent_app_type] => utility [patent_app_number] => 13/638010 [patent_app_country] => US [patent_app_date] => 2011-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6609 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13638010 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/638010
Method and apparatus for thin film module with dotted interconnects and vias May 26, 2011 Issued
Array ( [id] => 8730278 [patent_doc_number] => 20130075847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'MAGNETIC MEMORY' [patent_app_type] => utility [patent_app_number] => 13/636318 [patent_app_country] => US [patent_app_date] => 2011-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7545 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13636318 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/636318
MAGNETIC MEMORY Mar 15, 2011 Abandoned
Array ( [id] => 6104151 [patent_doc_number] => 20110186116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'METHOD FOR PRODUCING A SOLAR CELL HAVING A TWO-STAGE DOPING' [patent_app_type] => utility [patent_app_number] => 13/055754 [patent_app_country] => US [patent_app_date] => 2009-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5766 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20110186116.pdf [firstpage_image] =>[orig_patent_app_number] => 13055754 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/055754
METHOD FOR PRODUCING A SOLAR CELL HAVING A TWO-STAGE DOPING Jul 26, 2009 Abandoned
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