Search

Frances F Hamilton

Examiner (ID: 13152, Phone: (571)270-5726 , Office: P/3749 )

Most Active Art Unit
3762
Art Unit(s)
3743, 3749, 3762
Total Applications
727
Issued Applications
374
Pending Applications
47
Abandoned Applications
306

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17986271 [patent_doc_number] => 20220352308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => SELECTIVE POLYSILICON GROWTH FOR DEEP TRENCH POLYSILICON ISOLATION STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/867787 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867787
SELECTIVE POLYSILICON GROWTH FOR DEEP TRENCH POLYSILICON ISOLATION STRUCTURE Jul 18, 2022 Pending
Array ( [id] => 17949330 [patent_doc_number] => 20220336349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 17/857043 [patent_app_country] => US [patent_app_date] => 2022-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857043 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857043
Semiconductor packages Jul 3, 2022 Issued
Array ( [id] => 17949242 [patent_doc_number] => 20220336261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => METHOD OF FORMING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/809905 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17809905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/809905
METHOD OF FORMING SEMICONDUCTOR DEVICE Jun 29, 2022 Pending
Array ( [id] => 19314474 [patent_doc_number] => 12040300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Semiconductor package using hybrid-type adhesive [patent_app_type] => utility [patent_app_number] => 17/853870 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2092 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/853870
Semiconductor package using hybrid-type adhesive Jun 28, 2022 Issued
Array ( [id] => 17917652 [patent_doc_number] => 20220320048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => Wafer Level Integration of Passive Devices [patent_app_type] => utility [patent_app_number] => 17/848219 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848219
Wafer Level Integration of Passive Devices Jun 22, 2022 Pending
Array ( [id] => 17886390 [patent_doc_number] => 20220301868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => Forming Nitrogen-Containing Layers as Oxidation Blocking Layers [patent_app_type] => utility [patent_app_number] => 17/805563 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805563 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805563
Forming Nitrogen-Containing Layers as Oxidation Blocking Layers Jun 5, 2022 Pending
Array ( [id] => 17795589 [patent_doc_number] => 20220254681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => TRANSISTOR CELLS INCLUDING A DEEP VIA LINED WITH A DIELECTRIC MATERIAL [patent_app_type] => utility [patent_app_number] => 17/731149 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731149
TRANSISTOR CELLS INCLUDING A DEEP VIA LINED WITH A DIELECTRIC MATERIAL Apr 26, 2022 Pending
Array ( [id] => 17764959 [patent_doc_number] => 20220238572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Deep Trench Isolation Structures Resistant to Cracking [patent_app_type] => utility [patent_app_number] => 17/658704 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/658704
Deep Trench Isolation Structures Resistant to Cracking Apr 10, 2022 Pending
Array ( [id] => 17676969 [patent_doc_number] => 20220190136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/686504 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/686504
Semiconductor devices Mar 3, 2022 Issued
Array ( [id] => 19094043 [patent_doc_number] => 11955510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => High-efficiency capacitor structure [patent_app_type] => utility [patent_app_number] => 17/671040 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9960 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671040 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671040
High-efficiency capacitor structure Feb 13, 2022 Issued
Array ( [id] => 17536674 [patent_doc_number] => 20220115283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR PACKAGE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/559608 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -45 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559608 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559608
SEMICONDUCTOR PACKAGE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE Dec 21, 2021 Pending
Array ( [id] => 17477713 [patent_doc_number] => 20220085217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => Schottky Device and Method of Manufacturing the Same [patent_app_type] => utility [patent_app_number] => 17/456728 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456728
Schottky Device and Method of Manufacturing the Same Nov 28, 2021 Pending
Array ( [id] => 17463978 [patent_doc_number] => 20220077284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/526840 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526840
Semiconductor device Nov 14, 2021 Issued
Array ( [id] => 17676725 [patent_doc_number] => 20220189892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => HIGH FREQUENCY DEVICES INCLUDING ATTENUATING DIELECTRIC MATERIALS [patent_app_type] => utility [patent_app_number] => 17/454120 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454120
HIGH FREQUENCY DEVICES INCLUDING ATTENUATING DIELECTRIC MATERIALS Nov 8, 2021 Pending
Array ( [id] => 17402944 [patent_doc_number] => 20220045035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/510594 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510594
SEMICONDUCTOR DEVICES AND MANUFACTURING METHODS OF THE SAME Oct 25, 2021 Pending
Array ( [id] => 18999285 [patent_doc_number] => 11916141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Method for fabricating shield gate MOSFET [patent_app_type] => utility [patent_app_number] => 17/505662 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 3617 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/505662
Method for fabricating shield gate MOSFET Oct 19, 2021 Issued
Array ( [id] => 17389508 [patent_doc_number] => 20220037360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => Device, a Method Used in Forming a Circuit Structure, a Method Used in Forming an Array of Elevationally-Extending Transistors and a Circuit Structure Adjacent Thereto [patent_app_type] => utility [patent_app_number] => 17/504313 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504313 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504313
Device, a method used in forming a circuit structure, a method used in forming an array of elevationally-extending transistors and a circuit structure adjacent thereto Oct 17, 2021 Issued
Array ( [id] => 18258371 [patent_doc_number] => 20230085411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => GLASS CORE WITH CAVITY STRUCTURE FOR HETEROGENEOUS PACKAGING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/477323 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477323
GLASS CORE WITH CAVITY STRUCTURE FOR HETEROGENEOUS PACKAGING ARCHITECTURE Sep 15, 2021 Pending
Array ( [id] => 17477476 [patent_doc_number] => 20220084980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => PACKAGED SEMICONDUCTOR DEVICE HAVING IMPROVED RELIABILITY AND INSPECTIONABILITY AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/472207 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472207 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472207
PACKAGED SEMICONDUCTOR DEVICE HAVING IMPROVED RELIABILITY AND INSPECTIONABILITY AND MANUFACTURING METHOD THEREOF Sep 9, 2021 Pending
Array ( [id] => 17886503 [patent_doc_number] => 20220301981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/472181 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6462 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472181 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472181
SEMICONDUCTOR DIE INCLUDING THROUGH SUBSTRATE VIA BARRIER STRUCTURE AND METHODS FOR FORMING THE SAME Sep 9, 2021 Pending
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