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Francis John Bartuska

Examiner (ID: 13005)

Most Active Art Unit
3107
Art Unit(s)
3617, 3627, 3652, 3104, 2167, 2899, 3101, 3107
Total Applications
1653
Issued Applications
1415
Pending Applications
68
Abandoned Applications
170

Applications

Application numberTitle of the applicationFiling DateStatus
07/709559 METHOD AND APPARATUS FOR ARBITRATING CONFLICTS BY MONITORING NUMBER OF ACCESS REQUESTS PER UNIT OF TIME IN MULTIPORT MEMORY SYSTEMS Jun 2, 1991 Abandoned
07/700730 MEMORY CARD HAVING CONTROLLER PROVIDING ADJUSTABLE REFRESH TO A PLURALITY OF DRAMS May 14, 1991 Issued
07/692673 CIRCUITRY AND METHOD FOR ADDRESSING GLOBAL ARRAY ELEMENTS IN A DISTRIBUTED MEMORY, MULTIPLE PROCESSOR COMPUTER Apr 28, 1991 Abandoned
Array ( [id] => 3458232 [patent_doc_number] => 05420996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Data processing system having selective data save and address translation mechanism utilizing CPU idle period' [patent_app_type] => 1 [patent_app_number] => 7/691087 [patent_app_country] => US [patent_app_date] => 1991-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5242 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420996.pdf [firstpage_image] =>[orig_patent_app_number] => 691087 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/691087
Data processing system having selective data save and address translation mechanism utilizing CPU idle period Apr 24, 1991 Issued
07/689387 CACHE PAGE REPLACEMENT USING A LIFO CAST OUT Apr 21, 1991 Abandoned
Array ( [id] => 3110601 [patent_doc_number] => 05293608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'System and method for optimizing cache memory utilization by selectively inhibiting loading of data' [patent_app_type] => 1 [patent_app_number] => 7/688189 [patent_app_country] => US [patent_app_date] => 1991-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4185 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293608.pdf [firstpage_image] =>[orig_patent_app_number] => 688189 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/688189
System and method for optimizing cache memory utilization by selectively inhibiting loading of data Apr 18, 1991 Issued
Array ( [id] => 3024077 [patent_doc_number] => 05333292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Microcomputer for selectively accessing non-volatile memory and other storage unit in response to allocated address inputs' [patent_app_type] => 1 [patent_app_number] => 7/683222 [patent_app_country] => US [patent_app_date] => 1991-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1867 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/333/05333292.pdf [firstpage_image] =>[orig_patent_app_number] => 683222 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/683222
Microcomputer for selectively accessing non-volatile memory and other storage unit in response to allocated address inputs Apr 9, 1991 Issued
Array ( [id] => 3532755 [patent_doc_number] => 05490260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Solid-state RAM data storage for virtual memory computer using fixed-sized swap pages with selective compressed/uncompressed data store according to each data size' [patent_app_type] => 1 [patent_app_number] => 7/679530 [patent_app_country] => US [patent_app_date] => 1991-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 13574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/490/05490260.pdf [firstpage_image] =>[orig_patent_app_number] => 679530 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/679530
Solid-state RAM data storage for virtual memory computer using fixed-sized swap pages with selective compressed/uncompressed data store according to each data size Apr 1, 1991 Issued
Array ( [id] => 3078077 [patent_doc_number] => 05295255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Method and apparatus for programming a solid state processor with overleaved array memory modules' [patent_app_type] => 1 [patent_app_number] => 7/661049 [patent_app_country] => US [patent_app_date] => 1991-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9216 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/295/05295255.pdf [firstpage_image] =>[orig_patent_app_number] => 661049 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/661049
Method and apparatus for programming a solid state processor with overleaved array memory modules Feb 21, 1991 Issued
07/636276 A MICROPROCESSOR INCORPORATING CACHE MEMORY WITH SELECTIVE PURGE OPERATION Dec 30, 1990 Abandoned
Array ( [id] => 3108434 [patent_doc_number] => 05293491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-08 [patent_title] => 'Data processing system and memory controller for lock semaphore operations' [patent_app_type] => 1 [patent_app_number] => 7/635896 [patent_app_country] => US [patent_app_date] => 1990-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4391 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/293/05293491.pdf [firstpage_image] =>[orig_patent_app_number] => 635896 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/635896
Data processing system and memory controller for lock semaphore operations Dec 27, 1990 Issued
07/631833 METHOD FOR MANAGING ALLOCATION OF MEMORY SPACE Dec 20, 1990 Abandoned
Array ( [id] => 3064572 [patent_doc_number] => 05325500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Parallel processing units on a substrate, each including a column of memory' [patent_app_type] => 1 [patent_app_number] => 7/628916 [patent_app_country] => US [patent_app_date] => 1990-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 17210 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/325/05325500.pdf [firstpage_image] =>[orig_patent_app_number] => 628916 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/628916
Parallel processing units on a substrate, each including a column of memory Dec 13, 1990 Issued
Array ( [id] => 3089453 [patent_doc_number] => 05297242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'DMA controller performing data transfer by 2-bus cycle transfer manner' [patent_app_type] => 1 [patent_app_number] => 7/626957 [patent_app_country] => US [patent_app_date] => 1990-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4355 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/297/05297242.pdf [firstpage_image] =>[orig_patent_app_number] => 626957 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/626957
DMA controller performing data transfer by 2-bus cycle transfer manner Dec 12, 1990 Issued
07/624306 PORTABLE ELECTRONIC DEVICE WITH SELECTABLE RESUME FUNCTION Dec 6, 1990 Abandoned
07/622948 DATA STORAGE SYSTEM HAVING REMOVABLE DATA STORAGE MEDIA AND EQUIPPED TO READ A CONTROL PROGRAM FROM THE REMOVABLE MEDIA INTO STORAGE Dec 5, 1990 Abandoned
Array ( [id] => 2948186 [patent_doc_number] => 05247642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Apparatus for determining cacheability of a memory address to provide zero wait state operation in a computer system' [patent_app_type] => 1 [patent_app_number] => 7/622729 [patent_app_country] => US [patent_app_date] => 1990-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9443 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 764 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247642.pdf [firstpage_image] =>[orig_patent_app_number] => 622729 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/622729
Apparatus for determining cacheability of a memory address to provide zero wait state operation in a computer system Dec 4, 1990 Issued
Array ( [id] => 3024041 [patent_doc_number] => 05276834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Spare memory arrangement' [patent_app_type] => 1 [patent_app_number] => 7/621869 [patent_app_country] => US [patent_app_date] => 1990-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3273 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276834.pdf [firstpage_image] =>[orig_patent_app_number] => 621869 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/621869
Spare memory arrangement Dec 3, 1990 Issued
07/616540 TWO-LEVEL TLB HAVING THE SECOND LEVEL TLB IMPLEMENTED IN CACHE TAG RAMS Nov 20, 1990 Abandoned
07/612649 MULTIPLE COMPUTER SYSTEM WITH COMBINER/MEMORY INTERCONNECTION SYSTEM Nov 12, 1990 Abandoned
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